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1. 发明申请

US20100323429A1 Methods for purifying baculovirus 审中-公开
标题翻译：杆状病毒纯化方法
公开(公告)号：US20100323429A1
公开(公告)日：2010-12-23
申请号：US12081065
申请日：2008-04-10
申请人： Yu-Chen Hu , Guan-Yu Chen
发明人： Yu-Chen Hu , Guan-Yu Chen
IPC分类号： C12N7/02
CPC分类号： C12N7/00 , C12N2710/14051
摘要： The present invention provides a method for purifying baculovirus comprising: providing a baculovirus mixture containing a baculovirus and a liquid portion; replacing the liquid portion with a binding buffer by an ultrafiltration system to form a virus buffer; and purifying the baculovirus from the virus buffer using glycoprotein specific affinity chromatography. Therefore, use of the method of the present invention in the purification of baculovirus resulted in an enhanced discovery yield and improved purity of virus.
摘要翻译：本发明提供了一种用于纯化杆状病毒的方法，包括：提供含有杆状病毒和液体部分的杆状病毒混合物; 用超滤系统用结合缓冲液代替液体部分以形成病毒缓冲液; 并使用糖蛋白特异性亲和层析从病毒缓冲液纯化杆状病毒。因此，使用本发明的方法在杆状病毒的纯化中导致增加的发现产率和病毒的纯度提高。

2. 发明申请

US20130270693A1 Trace Layout Method in Bump-on-Trace Structures 有权
标题翻译：凸起跟踪结构中的跟踪布局方法
公开(公告)号：US20130270693A1
公开(公告)日：2013-10-17
申请号：US13445699
申请日：2012-04-12
申请人： Yu-Jen Tseng , Guan-Yu Chen , Sheng-Yu Wu , Chen-Hua Yu , Mirng-Ji Lii , Chen-Shien Chen , Tin-Hao Kuo
发明人： Yu-Jen Tseng , Guan-Yu Chen , Sheng-Yu Wu , Chen-Hua Yu , Mirng-Ji Lii , Chen-Shien Chen , Tin-Hao Kuo
IPC分类号： H01L23/498 , G06F17/50
CPC分类号： G06F17/5068 , H01L23/3192 , H01L23/49838 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/81 , H01L2224/0345 , H01L2224/03452 , H01L2224/03462 , H01L2224/0401 , H01L2224/05558 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05666 , H01L2224/05671 , H01L2224/1132 , H01L2224/11334 , H01L2224/1145 , H01L2224/11452 , H01L2224/11462 , H01L2224/11849 , H01L2224/13012 , H01L2224/13013 , H01L2224/13014 , H01L2224/13015 , H01L2224/13022 , H01L2224/131 , H01L2224/13111 , H01L2224/13139 , H01L2224/13147 , H01L2224/16105 , H01L2224/16225 , H01L2224/16227 , H01L2224/16238 , H01L2224/17104 , H01L2224/81191 , H01L2224/81385 , H01L2224/81444 , H01L2224/81815 , H01L2924/00014 , H01L2924/014 , H01L2924/00012 , H01L2924/01029 , H01L2924/01074 , H01L2224/1144
摘要： A method and device for preventing the bridging of adjacent metal traces in a bump-on-trace structure. An embodiment comprises determining the coefficient of thermal expansion (CTE) and process parameters of the package components. The design parameters are then analyzed and the design parameters may be modified based on the CTE and process parameters of the package components.
摘要翻译：一种用于防止在跟踪轨迹结构中的相邻金属迹线桥接的方法和装置。一个实施例包括确定包装部件的热膨胀系数（CTE）和工艺参数。然后分析设计参数，并且可以基于包装部件的CTE和工艺参数来修改设计参数。

3. 发明申请

US20110079708A1 SILICON PHOTODETECTION MODULE 审中-公开
标题翻译：硅光电模块
公开(公告)号：US20110079708A1
公开(公告)日：2011-04-07
申请号：US12754098
申请日：2010-04-05
申请人： Yue-Ming Hsin , Fang-Ping Chou , Guan-Yu Chen
发明人： Yue-Ming Hsin , Fang-Ping Chou , Guan-Yu Chen
IPC分类号： H01L31/102 , H03F3/08
CPC分类号： H03F3/08 , H01L31/103 , H01L31/1105
摘要： A silicon photo-detection module is disclosed, in which a silicon photodiode detection unit and a parasitical vertical bipolar junction transistor amplification unit can be simultaneously formed by a CMOS process. The silicon photo-detection module has a silicon substrate, a silicon photodiode detection unit comprising a positive portion and a negative portion, and a parasitical vertical bipolar junction transistor amplification unit comprising a collector, a base, and an emitter. The silicon photodiode detection unit and the parasitical vertical bipolar junction transistor amplification unit are formed on the silicon substrate by a CMOS process. Besides, the positive and negative portions of the silicon photodiode detection unit are electrically connected respectively with the base and the collector of the parasitical vertical bipolar junction transistor amplification unit.
摘要翻译：公开了一种硅光电检测模块，其中可以通过CMOS工艺同时形成硅光电二极管检测单元和寄生垂直双极结型晶体管放大单元。硅光检测模块具有硅衬底，包括正部分和负部分的硅光电二极管检测单元，以及包括集电极，基极和发射极的寄生垂直双极结型晶体管放大单元。通过CMOS工艺在硅衬底上形成硅光电二极管检测单元和寄生垂直双极结晶体管放大单元。此外，硅光电二极管检测单元的正极和负极分别与寄生垂直双极结型晶体管放大单元的基极和集电极电连接。

4. 发明申请

US20110186565A1 HEATING ASSEMBLY WITH INDUCTIVE COIL 审中-公开
标题翻译：加热组件与感应线圈
公开(公告)号：US20110186565A1
公开(公告)日：2011-08-04
申请号：US12940487
申请日：2010-11-05
申请人： Chien-Lung CHENG , Shyi-Ching Chern , Jim-Chwen Yeh , Guan-Yu Chen , Ching-Hung Hsieh
发明人： Chien-Lung CHENG , Shyi-Ching Chern , Jim-Chwen Yeh , Guan-Yu Chen , Ching-Hung Hsieh
IPC分类号： H05B6/10
CPC分类号： H05B6/10
摘要： A heating assembly includes two permanent magnets arranged in a spaced manner to define a path therebetween for passage of a plurality of stainless steel nails, and an inductive coil wound around an extending direction of the path in such a way that the inductive coil has a number of loops arranged along two opposite sides of the permanent magnets. Thus, when the stainless steel nails move through the path, the inductive coil can receive a low-intensity operation current to heat the stainless steel nails to a predetermined temperature.
摘要翻译：加热组件包括两个以间隔布置的永磁体，以在其间限定通路，用于通过多个不锈钢钉;以及绕路径延伸方向缠绕的感应线圈，使感应线圈具有数字的环绕着永磁体的两个相对侧布置。因此，当不锈钢钉移动通过路径时，感应线圈可以接收低强度的操作电流，以将不锈钢钉指向预定温度。

5. 发明授权

US08664041B2 Method for designing a package and substrate layout 有权
标题翻译：设计封装和基板布局的方法
公开(公告)号：US08664041B2
公开(公告)日：2014-03-04
申请号：US13445699
申请日：2012-04-12
申请人： Yu-Jen Tseng , Guan-Yu Chen , Sheng-Yu Wu , Chen-Hua Yu , Mirng-Ji Lii , Chen-Shien Chen , Tin-Hao Kuo
发明人： Yu-Jen Tseng , Guan-Yu Chen , Sheng-Yu Wu , Chen-Hua Yu , Mirng-Ji Lii , Chen-Shien Chen , Tin-Hao Kuo
IPC分类号： H01L21/44 , H01L21/48 , H01L21/50
CPC分类号： G06F17/5068 , H01L23/3192 , H01L23/49838 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/81 , H01L2224/0345 , H01L2224/03452 , H01L2224/03462 , H01L2224/0401 , H01L2224/05558 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05666 , H01L2224/05671 , H01L2224/1132 , H01L2224/11334 , H01L2224/1145 , H01L2224/11452 , H01L2224/11462 , H01L2224/11849 , H01L2224/13012 , H01L2224/13013 , H01L2224/13014 , H01L2224/13015 , H01L2224/13022 , H01L2224/131 , H01L2224/13111 , H01L2224/13139 , H01L2224/13147 , H01L2224/16105 , H01L2224/16225 , H01L2224/16227 , H01L2224/16238 , H01L2224/17104 , H01L2224/81191 , H01L2224/81385 , H01L2224/81444 , H01L2224/81815 , H01L2924/00014 , H01L2924/014 , H01L2924/00012 , H01L2924/01029 , H01L2924/01074 , H01L2224/1144
摘要： A method and device for preventing the bridging of adjacent metal traces in a bump-on-trace structure. An embodiment comprises determining the coefficient of thermal expansion (CTE) and process parameters of the package components. The design parameters are then analyzed and the design parameters may be modified based on the CTE and process parameters of the package components.
摘要翻译：一种用于防止在跟踪轨迹结构中的相邻金属迹线桥接的方法和装置。一个实施例包括确定包装部件的热膨胀系数（CTE）和工艺参数。然后分析设计参数，并且可以基于包装部件的CTE和工艺参数来修改设计参数。

6. 发明授权

US08598639B2 Si photodiode with symmetry layout and deep well bias in CMOS technology 有权
标题翻译：硅光电二极管具有对称布局和深阱偏压CMOS技术
公开(公告)号：US08598639B2
公开(公告)日：2013-12-03
申请号：US13039280
申请日：2011-03-02
申请人： Yue-Ming Hsin , Fang-Ping Chou , Ching-Wen Wang , Guan-Yu Chen
发明人： Yue-Ming Hsin , Fang-Ping Chou , Ching-Wen Wang , Guan-Yu Chen
IPC分类号： H01L31/113
CPC分类号： H01L31/103 , H01L27/1446
摘要： A silicon photodiode with symmetry layout and deep well bias in CMOS technology is provided. The silicon photodiode includes a substrate, a deep well, and a PN diode structure. The deep well is disposed on the substrate, where an extra bias is applied to the deep well. The region surrounded by the deep well forms the main body of the silicon photodiode. The PN diode structure is located in the region surrounded by the deep well, where the silicon photodiode has a symmetry layout. The deep well is adopted when fabricating the silicon photodiode, and the extra bias is applied to the deep well to eliminate the interference and effect of the substrate absorbing light, and further greatly improve speed and bandwidth. Furthermore, the silicon photodiode has a symmetry layout, so that uniform electric field distribution is achieved, and the interference of the substrate noise is also reduced.
摘要翻译：提供了CMOS技术中具有对称布局和深阱偏置的硅光电二极管。硅光电二极管包括衬底，深阱和PN二极管结构。深井设置在衬底上，其中对深井施加额外的偏压。由深阱包围的区域形成硅光电二极管的主体。 PN二极管结构位于由深阱包围的区域中，其中硅光电二极管具有对称布局。在制造硅光电二极管时采用深阱，并向深阱施加额外偏压，消除基板吸收光的干扰和影响，进一步大大提高速度和带宽。此外，硅光电二极管具有对称布局，从而实现均匀的电场分布，并且还降低了衬底噪声的干扰。

7. 发明申请

US20120175690A1 SI PHOTODIODE WITH SYMMETRY LAYOUT AND DEEP WELL BIAS IN CMOS TECHNOLOGY 有权
标题翻译：在CMOS技术中具有对称布局和深度偏移的SI光电
公开(公告)号：US20120175690A1
公开(公告)日：2012-07-12
申请号：US13039280
申请日：2011-03-02
申请人： Yue-Ming Hsin , Fang-Ping Chou , Ching-Wen Wang , Guan-Yu Chen
发明人： Yue-Ming Hsin , Fang-Ping Chou , Ching-Wen Wang , Guan-Yu Chen
IPC分类号： H01L31/113
CPC分类号： H01L31/103 , H01L27/1446
摘要： A silicon photodiode with symmetry layout and deep well bias in CMOS technology is provided. The silicon photodiode includes a substrate, a deep well, and a PN diode structure. The deep well is disposed on the substrate, where an extra bias is applied to the deep well. The region surrounded by the deep well forms the main body of the silicon photodiode. The PN diode structure is located in the region surrounded by the deep well, where the silicon photodiode has a symmetry layout. The deep well is adopted when fabricating the silicon photodiode, and the extra bias is applied to the deep well to eliminate the interference and effect of the substrate absorbing light, and further greatly improve speed and bandwidth. Furthermore, the silicon photodiode has a symmetry layout, so that uniform electric field distribution is achieved, and the interference of the substrate noise is also reduced.
摘要翻译：提供了CMOS技术中具有对称布局和深阱偏置的硅光电二极管。硅光电二极管包括衬底，深阱和PN二极管结构。深井设置在衬底上，其中对深井施加额外的偏压。由深阱包围的区域形成硅光电二极管的主体。 PN二极管结构位于由深阱包围的区域中，其中硅光电二极管具有对称布局。在制造硅光电二极管时采用深阱，并向深阱施加额外偏压，消除基板吸收光的干扰和影响，进一步大大提高速度和带宽。此外，硅光电二极管具有对称布局，从而实现均匀的电场分布，并且还降低了衬底噪声的干扰。

8. 发明申请

US20090324807A1 METHOD FOR FORMING A POROUS MATERIAL 审中-公开
标题翻译：形成多孔材料的方法
公开(公告)号：US20090324807A1
公开(公告)日：2009-12-31
申请号：US12147651
申请日：2008-06-27
申请人： Jih-Perng Leu , Kuo-Yuan Hsu , Hsin-Ling Hsu , Guan-Yu Chen , Nobuo Takasaka , Shi-Tsung Hung
发明人： Jih-Perng Leu , Kuo-Yuan Hsu , Hsin-Ling Hsu , Guan-Yu Chen , Nobuo Takasaka , Shi-Tsung Hung
IPC分类号： B05D5/12
CPC分类号： H01L23/5329 , C04B38/068 , H01L21/02203 , H01L21/31695 , H01L21/7682 , H01L2221/1047 , H01L2924/0002 , H01L2924/00
摘要： A method for forming a porous material is to mix a porous first basic material with a sacrificial material compatible with the first basic material to let the sacrificial material permeate into the pores of the first basic material to form a first finished product. Subsequently, the first finished product is mixed with a second basic material and heated over the vaporization temperature of the sacrificial material to let the ingredients of the second basic material change and increase viscous force and impossible to enter the pores of the first basic material. Simultaneously, the sacrificial material is heated and vaporized to exhaust out of the pores of the first basic material, disabling the second basic material to permeate into the pores of the first basic material and thus forming a second finished product for reserving the ingredients in the pores of the first basic material.
摘要翻译：用于形成多孔材料的方法是将多孔第一碱性材料与与第一碱性材料相容的牺牲材料混合，以使牺牲材料渗入第一基础材料的孔中以形成第一成品。随后，将第一成品与第二碱性材料混合并在牺牲材料的蒸发温度下加热，使第二碱性材料的成分发生变化并增加粘性力并且不可能进入第一基础材料的孔。同时，牺牲材料被加热和蒸发以排出第一碱性材料的孔隙，使得第二碱性物质不能渗透到第一碱性物质的孔中，从而形成第二成品，用于将成分保留在孔中的第一个基本材料。

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