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1. 发明授权

US08809933B2 Bit line structure, semiconductor device and method of forming the same 有权
标题翻译：位线结构，半导体器件及其形成方法
公开(公告)号：US08809933B2
公开(公告)日：2014-08-19
申请号：US12834212
申请日：2010-07-12
申请人： Guan-De Lee , Chien-Hung Liu , Shou-Wei Huang , Ying-Tso Chen
发明人： Guan-De Lee , Chien-Hung Liu , Shou-Wei Huang , Ying-Tso Chen
IPC分类号： H01L29/788 , H01L27/115 , H01L21/74
CPC分类号： H01L27/11568 , H01L21/743
摘要： A semiconductor device including a substrate, a plurality of stacked gate structures, a plurality of doped regions, a plurality of liner layers, a plurality of conductive layers, a plurality of dielectric layers and a plurality of word lines is provided. The substrate has a plurality of trenches therein. The stacked gate structures are on the substrate between the trenches. The doped regions are in the substrate at sidewalls or bottoms of the trenches. The liner layers are on at least a portion of sidewalls of the stacked gate structures and on sidewalls of the trenches. The conductive layers are in the trenches and electrically connected to the doped regions. The dielectric layers are on the conductive layers and between the stacked gate structures. The word lines are on the substrate and electrically connected to the stacked gate structures.
摘要翻译：提供了包括衬底，多个堆叠栅极结构，多个掺杂区域，多个衬底层，多个导电层，多个电介质层和多个字线的半导体器件。衬底中具有多个沟槽。堆叠的栅极结构在沟槽之间的衬底上。掺杂区域在沟槽的侧壁或底部的衬底中。衬垫层位于堆叠的栅极结构的侧壁的至少一部分和沟槽的侧壁上。导电层位于沟槽中并与掺杂区电连接。电介质层位于导电层之间并且在堆叠的栅极结构之间。字线在基板上并电连接到堆叠的栅极结构。

2. 发明申请

US20110198698A1 BIT LINE STRUCTURE, SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME 有权
标题翻译：位线结构，半导体器件及其形成方法
公开(公告)号：US20110198698A1
公开(公告)日：2011-08-18
申请号：US12834212
申请日：2010-07-12
申请人： GUAN-DE LEE , Chien-Hung Liu , Shou-Wei Huang , Ying-Tso Chen
发明人： GUAN-DE LEE , Chien-Hung Liu , Shou-Wei Huang , Ying-Tso Chen
IPC分类号： H01L27/088 , H01L21/8234 , H01L23/48
CPC分类号： H01L27/11568 , H01L21/743
摘要： A semiconductor device including a substrate, a plurality of stacked gate structures, a plurality of doped regions, a plurality of liner layers, a plurality of conductive layers, a plurality of dielectric layers and a plurality of word lines is provided. The substrate has a plurality of trenches therein. The stacked gate structures are on the substrate between the trenches. The doped regions are in the substrate at sidewalls or bottoms of the trenches. The liner layers are on at least a portion of sidewalls of the stacked gate structures and on sidewalls of the trenches. The conductive layers are in the trenches and electrically connected to the doped regions. The dielectric layers are on the conductive layers and between the stacked gate structures. The word lines are on the substrate and electrically connected to the stacked gate structures.
摘要翻译：提供了包括衬底，多个堆叠栅极结构，多个掺杂区域，多个衬底层，多个导电层，多个电介质层和多个字线的半导体器件。衬底中具有多个沟槽。堆叠的栅极结构在沟槽之间的衬底上。掺杂区域在沟槽的侧壁或底部的衬底中。衬垫层位于堆叠的栅极结构的侧壁的至少一部分和沟槽的侧壁上。导电层位于沟槽中并与掺杂区电连接。电介质层位于导电层之间并且在堆叠的栅极结构之间。字线在基板上并电连接到堆叠的栅极结构。

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