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    • 1. 发明授权
    • Formatting of recompressed data in an MPEG decoder
    • 在MPEG解码器中格式化再压缩数据
    • US06594315B1
    • 2003-07-15
    • US09319862
    • 1999-06-11
    • Mark Alan SchultzGreg Alan Kranawetter
    • Mark Alan SchultzGreg Alan Kranawetter
    • H04B166
    • H04N5/4401H03M7/40H04N5/46H04N19/186H04N19/40H04N19/42H04N19/423H04N19/428H04N19/59H04N19/60H04N19/61H04N19/895H04N19/90H04N19/91
    • An MPEG decoder in a high definition television receiver decodes and decompresses MPEG coded data to produce decompressed image pixel blocks, and includes a motion compensation network coupled to a frame memory to produce finally decoded pixel data for display. The decompressed MPEG data is recompressed by plural parallel recompressors prior to storage in frame memory. Each recompressor receives a datastream of interleaved pixel data, and predicts and compresses interleaved pixel values during each clock cycle, respectively. One of the recompressors is de-energized in a reduced data processing mode when pixel data is subsampled prior to recompression. Subsampled data is re-ordered prior to recompression. Multiple parallel decompressors coupled to the frame memory provide pixel data to the motion processing network. A control unit, insures an uninterrupted interleaved data flow to the decompressors by repeating last valid data when source data is interrupted.
    • 高清晰度电视接收机中的MPEG解码器对MPEG编码数据进行解码和解压缩以产生解压缩的图像像素块,并且包括耦合到帧存储器的运动补偿网络,以产生用于显示的最终解码的像素数据。 解压缩的MPEG数据在存储在帧存储器中之前被多个并行的再压缩机重新压缩。 每个重新压缩器接收交错像素数据的数据流,并分别在每个时钟周期期间预测和压缩交错像素值。 当在重新压缩之前对像素数据进行二次采样时,其中一个再压缩器在减小的数据处理模式中被断电。 在重新压缩之前重新排序采样数据。 耦合到帧存储器的多个并行解压缩器向运动处理网络提供像素数据。 控制单元通过在源数据中断时重复最后的有效数据来确保不间断的交错数据流到解压缩器。
    • 3. 发明授权
    • Video decoder with interleaved data processing
    • 具有交错数据处理的视频解码器
    • US06496537B1
    • 2002-12-17
    • US09319861
    • 1999-06-11
    • Greg Alan KranawetterMark Alan Schultz
    • Greg Alan KranawetterMark Alan Schultz
    • H04N736
    • H04N7/015H03M7/40H04N5/4401H04N5/46H04N19/186H04N19/40H04N19/42H04N19/423H04N19/428H04N19/44H04N19/59H04N19/60H04N19/61H04N19/895H04N19/90H04N19/91
    • An MPEG decoder in a high definition television receiver decodes and decompresses MPEG coded data to produce decompressed image pixel blocks, and includes a motion compensation network coupled to a frame memory to produce finally decoded pixel data for display. The decompressed MPEG data is recompressed by plural parallel recompressors prior to storage in frame memory. Each recompressor receives a datastream of interleaved pixel data, and predicts and compresses interleaved pixel values during each clock cycle, respectively. One of the recompressors is de-energized in a reduced data processing mode when pixel data is subsampled prior to recompression. Subsampled data is re-ordered prior to recompression. Multiple parallel decompressors coupled to the frame memory provide pixel data to the motion processing network. A control unit insures an uninterrupted interleaved data flow to the decompressors by repeating last valid data when source data is interrupted.
    • 高清晰度电视接收机中的MPEG解码器对MPEG编码数据进行解码和解压缩以产生解压缩的图像像素块,并且包括耦合到帧存储器的运动补偿网络,以产生用于显示的最终解码的像素数据。 解压缩的MPEG数据在存储在帧存储器中之前被多个并行的再压缩机重新压缩。 每个重新压缩器接收交错像素数据的数据流,并分别在每个时钟周期期间预测和压缩交错像素值。 当在重新压缩之前对像素数据进行二次采样时,其中一个再压缩器在减小的数据处理模式中被断电。 在重新压缩之前重新排序采样数据。 耦合到帧存储器的多个并行解压缩器向运动处理网络提供像素数据。 控制单元通过在源数据被中断时重复最后的有效数据来保证对解压缩器的不间断的交错数据流。
    • 5. 发明授权
    • Delay correction circuit
    • 延迟校正电路
    • US5963267A
    • 1999-10-05
    • US717093
    • 1996-09-20
    • Greg Alan Kranawetter
    • Greg Alan Kranawetter
    • H04N5/12H04L7/02H04N5/95H04N5/956H04N5/04
    • H04N5/956
    • A delay correction circuit includes a source of a clock signal and a source of a timing signal asynchronous with the clock signal. A timing signal detector is responsive to the clock signal and the timing signal, and is properly operative only when the timing signal is stable for a predetermined time period around the clock signal. A control circuit conditions utilization circuitry to operate after a delay time after the timing signal is detected. Adjusting circuitry conditions the control circuit to adjust the delay time if the timing signal was not stable within the predetermined time period.
    • 延迟校正电路包括时钟信号源和与时钟信号异步的定时信号源。 定时信号检测器响应于时钟信号和定时信号,并且仅在定时信号在时钟信号周围的预定时间周期内稳定时适当地操作。 控制电路使利用电路在检测到定时信号之后的延迟时间之后进行操作。 如果定时信号在预定时间段内不稳定,则调节电路使控制电路调节延迟时间。
    • 6. 发明授权
    • Parallel decoding of interleaved data streams within an MPEG decoder
    • MPEG解码器内交错数据流的并行解码
    • US06970504B1
    • 2005-11-29
    • US09319324
    • 1997-12-15
    • Greg Alan KranawetterMark Alan Schultz
    • Greg Alan KranawetterMark Alan Schultz
    • H04B1/66H04N7/26H04N7/50
    • H04N19/428H04N19/436H04N19/44H04N19/61
    • An MPEG decoder in a high definition television receiver decodes and decompresses MPEG coded data to produce decompressed image pixel blocks, and includes a motion compensation network coupled to a frame memory to produce finally decoded pixel data for display. The decompressed MPEG data is recompressed by plural parallel recompressors prior to storage in frame memory. Each recompressor receives a datastream of interleaved pixel data, and predicts and compresses interleaved pixel values during each clock cycle, respectively. One of the recompressors is de-energized in a reduced data processing mode when pixel data is subsampled prior to recompression. Subsampled data is re-ordered prior to recompression. Multiple parallel decompressors coupled to the frame memory provide pixel data to the motion processing network. A control unit insures an uninterrupted interleaved data flow to the decompressors by repeating last valid data when source data is interrupted.
    • 高清晰度电视接收机中的MPEG解码器对MPEG编码数据进行解码和解压缩以产生解压缩的图像像素块,并且包括耦合到帧存储器的运动补偿网络,以产生用于显示的最终解码的像素数据。 解压缩的MPEG数据在存储在帧存储器中之前被多个并行的再压缩机重新压缩。 每个重新压缩器接收交错像素数据的数据流,并分别在每个时钟周期期间预测和压缩交错像素值。 当在重新压缩之前对像素数据进行二次采样时,其中一个再压缩器在减小的数据处理模式中被断电。 在重新压缩之前重新排序采样数据。 耦合到帧存储器的多个并行解压缩器向运动处理网络提供像素数据。 控制单元通过在源数据被中断时重复最后的有效数据来保证对解压缩器的不间断的交错数据流。
    • 7. 发明授权
    • Selective compression network in an MPEG compatible decoder
    • MPEG兼容解码器中的选择性压缩网络
    • US06879631B1
    • 2005-04-12
    • US09319763
    • 1997-12-15
    • Mark Alan SchultzGreg Alan Kranawetter
    • Mark Alan SchultzGreg Alan Kranawetter
    • H03M7/30H04N7/12H04N7/26
    • H04N19/436H03M7/30H04N19/428H04N19/44
    • An MPEG decoder in a high definition television receiver decodes and decompresses MPEG coded data to produce decompressed image pixel blocks, and includes a motion compensation network coupled to a frame memory to produce finally decoded pixel data for display. The decompressed MPEG data is recompressed by plural parallel recompressors prior to storage in frame memory. Each recompressor receives a datastream of interleaved pixel data, and predicts and compresses interleaved pixel values during each clock cycle, respectively. One of the recompressors is de-energized in a reduced data processing mode when pixel data is subsampled prior to recompression. Subsampled data is re-ordered prior to recompression. Multiple parallel decompressors coupled to the frame memory provide pixel data to the motion processing network. A control unit insures an uninterrupted interleaved data flow to the decompressors by repeating last valid data when source data is interrupted.
    • 高清晰度电视接收机中的MPEG解码器对MPEG编码数据进行解码和解压缩以产生解压缩的图像像素块,并且包括耦合到帧存储器的运动补偿网络,以产生用于显示的最终解码的像素数据。 解压缩的MPEG数据在存储在帧存储器中之前被多个并行的再压缩机重新压缩。 每个重新压缩器接收交错像素数据的数据流,并分别在每个时钟周期期间预测和压缩交错像素值。 当在重新压缩之前对像素数据进行二次采样时,其中一个再压缩器在减小的数据处理模式中被断电。 在重新压缩之前重新排序采样数据。 耦合到帧存储器的多个并行解压缩器向运动处理网络提供像素数据。 控制单元通过在源数据被中断时重复最后的有效数据来保证对解压缩器的不间断的交错数据流。
    • 8. 发明授权
    • System for maintaining datastream continuity in the presence of disrupted source data
    • 在存在中断的源数据的情况下维护数据流连续性的系统
    • US06377628B1
    • 2002-04-23
    • US09319762
    • 1999-06-11
    • Mark Alan SchultzGreg Alan Kranawetter
    • Mark Alan SchultzGreg Alan Kranawetter
    • H04B166
    • H03M7/40H04N5/4401H04N5/46H04N19/186H04N19/40H04N19/42H04N19/423H04N19/428H04N19/436H04N19/59H04N19/60H04N19/61H04N19/895H04N19/90H04N19/91
    • An MPEG decoder in a high definition television receiver decodes and decompresses MPEG coded data to produce decompressed image pixel blocks, and includes a motion compensation network coupled to a frame memory to produce finally decoded pixel data for display. The decompressed MPEG data is recompressed by plural parallel recompressors prior to storage in frame memory. Each recompressor receives a datastream of interleaved pixel data, and predicts and compresses interleaved pixel values during each clock cycle, respectively. One of the recompressors is de-energized in a reduced data processing mode when pixel data is subsampled prior to recompression. Subsampled data is re-ordered prior to recompression. Multiple parallel decompressors coupled to the frame memory provide pixel data to the motion processing network. A control unit insures an uninterrupted interleaved data flow to the decompressors by repeating last valid data when source data is interrupted.
    • 高分辨率电视接收机中的MPEG解码器对MPEG编码数据进行解码和解压缩以产生解压缩的图像像素块,并且包括耦合到帧存储器的运动补偿网络,以产生用于显示的最终解码的像素数据。 解压缩的MPEG数据在存储在帧存储器中之前被多个并行的再压缩机重新压缩。 每个重新压缩器接收交错像素数据的数据流,并分别在每个时钟周期期间预测和压缩交错像素值。 当在重新压缩之前对像素数据进行二次采样时,其中一个再压缩器在减小的数据处理模式中被断电。 在重新压缩之前重新排序采样数据。 耦合到帧存储器的多个并行解压缩器向运动处理网络提供像素数据。 控制单元通过在源数据被中断时重复最后的有效数据来保证对解压缩器的不间断的交错数据流。
    • 9. 发明授权
    • System and method for minimizing clock cycles lost to overhead data in a video decoder
    • 用于最小化视频解码器中的开销数据丢失的时钟周期的系统和方法
    • US06205250B1
    • 2001-03-20
    • US09140993
    • 1998-08-27
    • Greg Alan Kranawetter
    • Greg Alan Kranawetter
    • G06K964
    • H04N19/42H04N19/44H04N19/61
    • A video processing device capable of minimizing clock cycles lost to overhead information includes an encoder for generating first and second groups of overhead bits. The first group includes a fixed number of overhead bits and the second group includes a variable number of overhead bits. A shift register receives pixel data from a data source, receives the second group of overhead bits from the encoder, and provides output of the pixel data and the second group of overhead bits. A multiplexer receives the pixel data and the second group of overhead bits from the shift register, receives the first group of overhead bits from the encoder, and provides output of the pixel data and the first and second groups of overhead bits which are then combined in an output register.
    • 能够最小化对开销信息丢失的时钟周期的视频处理装置包括用于产生第一组和第二组开销比特的编码器。 第一组包括固定数量的开销比特,第二组包括可变数量的开销比特。 移位寄存器从数据源接收像素数据,从编码器接收第二组开销比特,并提供像素数据和第二组开销比特的输出。 多路复用器从移位寄存器接收像素数据和第二组开销比特,从编码器接收第一组开销比特,并提供像素数据和第一组和第二组开销比特的输出,然后将其组合在 输出寄存器。