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1. 发明授权

US4394763A Error-correcting system 失效
标题翻译：纠错系统
公开(公告)号：US4394763A
公开(公告)日：1983-07-19
申请号：US261181
申请日：1981-04-24
申请人： Genzo Nagano , Masao Takahashi
发明人： Genzo Nagano , Masao Takahashi
IPC分类号： G06F11/08 , G06F11/10 , G06F11/16 , G06F12/16 , G11C29/00
CPC分类号： G11C29/70 , G06F11/1024
摘要： An error-correcting system is disclosed, which is located between a main memory and a central processing unit. The system includes a relief bit memory, an ECC or Error Correction Code logic circuit, a switching circuit and a correction controlling circuit. The ECC logic circuit detects the occurrence of a soft error and a hard error. When a hard error occurs in the memory, the defective memory cell thereof is switched to the relief bit memory. Accordingly, data to be written into the main memory or the relief bit memory is switched by means of the switching circuit. Similarly, data to be read from the main memory or the relief bit memory is also switched by the switching circuit. The data to be stored in the relief bit memory is validated by means of the ECC logic circuit and the switching circuit. Further, the (n+1)-bit soft and hard errors are reduced to n-bit soft and hard errors by means of the ECC logic circuit and the switching circuit.
摘要翻译： PCT No.PCT / JP80 / 00199 Sec。 371日期：1981年5月1日 102（e）日期1981年4月24日PCT提交1980年8月29日PCT公布。出版物WO81 / 00641 日期：1981年3月5日。公开了一种位于主存储器和中央处理单元之间的纠错系统。该系统包括浮点位存储器，ECC或纠错码逻辑电路，开关电路和校正控制电路。 ECC逻辑电路检测到软错误和硬错误的发生。当存储器发生硬错误时，其有缺陷的存储单元被切换到浮点位存储器。因此，通过开关电路来切换要写入主存储器或浮点位存储器的数据。类似地，由主存储器或浮点位存储器读取的数据也由切换电路切换。存储在浮点位存储器中的数据通过ECC逻辑电路和开关电路来验证。此外，通过ECC逻辑电路和开关电路将（n + 1）位的软和硬错误减少到n位软和硬错误。

2. 发明授权

US4115851A Memory access control system 失效
标题翻译：内存访问控制系统
公开(公告)号：US4115851A
公开(公告)日：1978-09-19
申请号：US785104
申请日：1977-04-06
申请人： Genzo Nagano , Hiroshi Nakamura , Yukio Sohma
发明人： Genzo Nagano , Hiroshi Nakamura , Yukio Sohma
IPC分类号： G06F3/06 , G06F9/52 , G06F12/00 , G06F12/06 , G06F13/16 , G06F15/16 , G06F15/177 , G06F13/00
CPC分类号： G06F13/1605 , G06F13/1631
摘要： A memory access control system is provided between one or more accessing devices and a main memory composed of a plurality of independently accessible logical storages, and receives a request from the accessing device and, based on the status of the main memory, permits access to one of the logical storages. The memory access control system comprises a shift register, composed of stages corresponding to the cycle time of the main memory, for storing address information sufficient for identifying a busy one of the logical storages and for sequentially shifting the stored content in synchronism with a clock signal, and a comparator circuit for comparing the content of each stage of the shift register with address information of the logical storage designated based on the request from the accessing device, receiving the request based on the result of the comparison, and generating a control signal for accessing the designated logical storage. Using the shift register, one of the logical storages to be accessed can be checked whether it is busy or not, so that even if the number of logical storages is increased with an increase of the capacity of the main memory, the scale of the memory access control system is not enlarged. The shift register also has stored therein the codes of operations, the codes of the accessing devices, etc., and is capable of identifying the accessing device to which data read out from the main memory is to be sent back, and of achieving a partial write control.
摘要翻译：在一个或多个访问设备和由多个可独立访问的逻辑存储器组成的主存储器之间提供存储器访问控制系统，并且从接入设备接收请求，并且基于主存储器的状态允许访问一个的逻辑存储。存储器访问控制系统包括一个移位寄存器，由与主存储器的周期时间相对应的级组成，用于存储足以识别逻辑存储器中的一个的地址信息，并且与时钟信号同步顺序移位存储的内容以及比较电路，用于将移位寄存器的各级的内容与基于来自访问装置的请求指定的逻辑存储器的地址信息进行比较，基于比较结果接收请求，生成控制信号访问指定的逻辑存储。使用移位寄存器，可以检查要访问的逻辑存储器中的一个是否是忙，使得即使逻辑存储器的数量随着主存储器的容量的增加而增加，存储器的规模门禁系统不扩大。移位寄存器还存储有操作代码，访问设备的代码等，并且能够识别要从主存储器读出的数据被发送回的访问设备，并且实现部分写控制。

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