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1. 发明授权

US07328384B1 Method and apparatus using device defects as an identifier 有权
标题翻译：使用设备缺陷作为标识符的方法和设备
公开(公告)号：US07328384B1
公开(公告)日：2008-02-05
申请号：US11238781
申请日：2005-09-29
申请人： Chidamber R. Kulkarni , Gary R. Lawman , Stephen M. Trimberger
发明人： Chidamber R. Kulkarni , Gary R. Lawman , Stephen M. Trimberger
IPC分类号： G01R31/28
CPC分类号： G01R31/318519
摘要： A method and apparatus that uses device defects as an identifier. Data is written to memory of an integrated circuit. Defects are identified based upon the writing of the data. An identifier for the IC is then derived using the identification of the defects.
摘要翻译：使用设备缺陷作为标识符的方法和装置。数据被写入集成电路的存储器。缺陷根据数据的写入来识别。然后使用缺陷的识别导出IC的标识符。

2. 发明授权

US6044025A PROM with built-in JTAG capability for configuring FPGAs 有权
标题翻译： PROM具有内置的JTAG功能，用于配置FPGA
公开(公告)号：US6044025A
公开(公告)日：2000-03-28
申请号：US244684
申请日：1999-02-04
申请人： Gary R. Lawman
发明人： Gary R. Lawman
IPC分类号： G01R31/3185 , G06F17/50 , G11C7/00
CPC分类号： G01R31/318519 , G06F17/5054
摘要： The invention provides a structure and method for configuring an FPGA from a PROM using a boundary scan chain. A PROM is provided that comprises JTAG circuitry. Configuration data is stored in the PROM memory as in known PROMs. When the data is retrieved from the PROM memory it is provided on a standard JTAG Test Access Port (TAP). The JTAG-compatible PROM is included as part of a JTAG scan chain, preferably directly preceding the FPGA to be configured by the PROM. The PROM can be controlled either externally or via JTAG commands received down the scan chain. Therefore, a reconfiguration of the FPGA can be initiated via standard JTAG commands. In one embodiment, the PROM itself is programmed with the FPGA configuration data using the JTAG TAP port.
摘要翻译：本发明提供了一种使用边界扫描链从PROM配置FPGA的结构和方法。提供了一个包含JTAG电路的PROM。配置数据与已知的PROM一样存储在PROM存储器中。当从PROM存储器检索数据时，它被提供在标准JTAG测试访问端口（TAP）上。 JTAG兼容的PROM作为JTAG扫描链的一部分，优选在由PROM配置的FPGA之前。 PROM可以从外部控制，也可以通过沿扫描链接收的JTAG命令进行控制。因此，可以通过标准JTAG命令启动FPGA的重新配置。在一个实施例中，PROM本身使用JTAG TAP端口用FPGA配置数据编程。

3. 发明授权

US06381732B1 FPGA customizable to accept selected macros 有权
标题翻译： FPGA可自定义接受选定的宏
公开(公告)号：US06381732B1
公开(公告)日：2002-04-30
申请号：US09924357
申请日：2001-08-07
申请人： James L. Burnham , Gary R. Lawman , Joseph D. Linoff
发明人： James L. Burnham , Gary R. Lawman , Joseph D. Linoff
IPC分类号： H03K19177
CPC分类号： G06F21/76
摘要： A field programmable gate array (FPGA) is provided that can selectively accept or reject selected software (macros). Specifically, configuration data for the FPGA is passed through a configuration port to a decoder. The decoder processes the configuration data to detect locked macros. If a locked macro is detected, the decoder attempts to unlock the locked macro using one or more keys stored in a key table of the FGPA. If an appropriate key is in the key table, the decoder unlocks the locked macro to configure the FPGA. The keys can be pre-programmed into the FGPA by the macro vendor. If configuration data containing a locked macro is used with an FPGA without the appropriate key, configuration of the FPGA fails.
摘要翻译：提供了可选择性地接受或拒绝所选软件（宏）的现场可编程门阵列（FPGA）。具体来说，FPGA的配置数据通过配置端口传递给解码器。解码器处理配置数据以检测锁定的宏。如果检测到锁定的宏，则解码器尝试使用存储在FGPA的密钥表中的一个或多个密钥解锁锁定的宏。如果密钥表中有一个相应的密钥，解码器解锁锁定的宏以配置FPGA。密钥可以由宏供应商预编程到FGPA中。如果包含锁定宏的配置数据在没有适当键的情况下与FPGA一起使用，则FPGA的配置将失败。

4. 发明授权

US06357037B1 Methods to securely configure an FPGA to accept selected macros 有权
标题翻译：安全配置FPGA以接受选定宏的方法
公开(公告)号：US06357037B1
公开(公告)日：2002-03-12
申请号：US09232022
申请日：1999-01-14
申请人： James L. Burnham , Gary R. Lawman , Joseph D. Linoff
发明人： James L. Burnham , Gary R. Lawman , Joseph D. Linoff
IPC分类号： G06F1750
CPC分类号： G06F21/76 , G06F17/5054
摘要： A method is provided for configuring an FPGA to accept or reject selected software (macros). Specifically, if an end user desires to use a locked macro from a first macro vendor a locked macro from a second macro vendor in the same FPGA, a key manager prepares a keyed FPGA for the end user by pre-programming an FPGA with a first key, which is configured to unlock the first locked macro, and a second key, which is configured to unlock the second locked macro. The key manager obtains the first key from the first macro vendor and the second key from the second macro vendor. The keys are stored in a key table of the FPGA that is write-only from outside the FPGA. The end user pays a fee to the key manager for the keyed macro, but is not given access to the keys. The key manager apportions the fee from the end user and distributes appropriate licensing fees to the first macro vendor and the second macro vendor.
摘要翻译：提供了一种用于配置FPGA以接受或拒绝所选软件（宏）的方法。具体来说，如果终端用户希望使用来自第一宏供应商的锁定宏来自同一FPGA中的第二宏供应商的锁定宏，则密钥管理器通过对第一个FPGA的预编程来为最终用户准备一个带键的FPGA 键，其被配置为解锁第一锁定宏，以及第二键，其被配置为解锁第二锁定宏。密钥管理器从第一个宏供应商获取第一个密钥，从第二个宏供应商获取第二个密钥。密钥存储在FPGA的关键表中，FPGA的外部是只写的。最终用户向键控宏的密钥管理者支付费用，但是不能访问密钥。主要经理从最终用户分配费用，并向第一个宏供应商和第二个宏供应商分配适当的许可费用。

5. 发明授权

US06324676B1 FPGA customizable to accept selected macros 有权
标题翻译： FPGA可自定义接受选定的宏
公开(公告)号：US06324676B1
公开(公告)日：2001-11-27
申请号：US09232021
申请日：1999-01-14
申请人： James L. Burnham , Gary R. Lawman , Joseph D. Linoff
发明人： James L. Burnham , Gary R. Lawman , Joseph D. Linoff
IPC分类号： G06F1750
CPC分类号： G06F21/76
摘要： A field programmable gate array (FPGA) is provided that can selectively accept or reject selected software (macros). Specifically, configuration data for the FPGA is passed through a configuration port to a decoder. The decoder processes the configuration data to detect locked macros. If a locked macro is detected, the decoder attempts to unlock the locked macro using one or more keys stored in a key table of the FGPA. If an appropriate key is in the key table, the decoder unlocks the locked macro to configure the FPGA. The keys can be pre-programmed into the FGPA by the macro vendor. If configuration data containing a locked macro is used with an FPGA without the appropriate key, configuration of the FPGA fails.
摘要翻译：提供了可选择性地接受或拒绝所选软件（宏）的现场可编程门阵列（FPGA）。具体来说，FPGA的配置数据通过配置端口传递给解码器。解码器处理配置数据以检测锁定的宏。如果检测到锁定的宏，则解码器尝试使用存储在FGPA的密钥表中的一个或多个密钥解锁锁定的宏。如果密钥表中有一个相应的密钥，解码器解锁锁定的宏以配置FPGA。密钥可以由宏供应商预编程到FGPA中。如果包含锁定宏的配置数据在没有适当键的情况下与FPGA一起使用，则FPGA的配置将失败。

6. 发明授权

US6023565A Method for configuring circuits over a data communications link 失效
标题翻译：通过数据通信链路配置电路的方法
公开(公告)号：US6023565A
公开(公告)日：2000-02-08
申请号：US805378
申请日：1997-02-24
申请人： Gary R. Lawman , Joseph D. Linoff , Robert W. Wells
发明人： Gary R. Lawman , Joseph D. Linoff , Robert W. Wells
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： A method of specifying design parameters is provided for configuring circuits for programmable ICs. A design database describing a circuit is displayed in table-based format on a computer screen display. The design database may include a memory map including data to be placed in bit-storage space in the target programmable IC. This design database requires no schematics or HDL description of the circuit, even for complicated application-specific circuits. The desired parameters are entered by the user, typically using toggle buttons, pull-down menus, or keyboard entry. The selected parameters are then entered into the design database, thereby configuring the design database in accordance with the selected parameters. Next, the design database is transmitted over a data communications link such as the internet to a second computer, on which the compilation software resides. The design is then compiled and the resulting netlist is transmitted back to the originating computer. In one embodiment, a schematic symbol or HDL instantiation is also generated by the second computer, and transmitted back to the originating computer.
摘要翻译：提供了一种指定设计参数的方法，用于配置可编程IC的电路。描述电路的设计数据库在计算机屏幕显示器上以基于表格的格式显示。设计数据库可以包括存储图，包括要放置在目标可编程IC中的位存储空间中的数据。该设计数据库不需要电路的原理图或HDL描述，即使对于复杂的应用特定电路也是如此。所需的参数由用户输入，通常使用切换按钮，下拉菜单或键盘输入。然后将选定的参数输入设计数据库，从而根据所选参数配置设计数据库。接下来，将设计数据库通过诸如因特网的数据通信链路传送到编译软件所在的第二计算机。然后编译设计，并将所得到的网表传回原始计算机。在一个实施例中，示意符号或HDL实例化也由第二计算机产生，并被发送回始发计算机。

7. 发明授权

US06882182B1 Tunable clock distribution system for reducing power dissipation 有权
标题翻译：可调谐时钟分配系统，用于降低功耗
公开(公告)号：US06882182B1
公开(公告)日：2005-04-19
申请号：US10669589
申请日：2003-09-23
申请人： Robert O. Conn , Gary R. Lawman , Christopher H. Kingsley , Austin H. Lesea
发明人： Robert O. Conn , Gary R. Lawman , Christopher H. Kingsley , Austin H. Lesea
IPC分类号： G06F1/10 , H03K3/012 , H03K19/00
CPC分类号： G06F1/10 , H03K3/012
摘要： A tunable clock distribution system is used to minimize the power dissipation of a clock distribution network in an integrated circuit. The tunable clock distribution system provides a tunable inductance on the clock distribution network to adjust a resonant frequency in the tunable clock distribution system. The inductance is tuned so that the resonant frequency of the tunable clock distribution system approaches the frequency of the clock signal on the clock distribution network. As the resonant frequency of the tunable clock distribution system approaches the frequency of the clock signal, the power dissipation of the clock distribution network decreases. Some embodiments also provide a tunable capacitance on the clock distribution network to adjust the resonant frequency of the tunable clock distribution system.
摘要翻译：可调谐时钟分配系统用于最小化集成电路中时钟分配网络的功耗。可调时钟分配系统在时钟分配网络上提供可调电感，以调节可调时钟分配系统中的谐振频率。调谐电感使得可调谐时钟分配系统的谐振频率接近时钟分配网络上时钟信号的频率。随着可调谐时钟分配系统的谐振频率接近时钟信号的频率，时钟分配网络的功耗降低。一些实施例还在时钟分配网络上提供可调谐电容以调节可调时钟分配系统的谐振频率。

8. 发明授权

US06301695B1 Methods to securely configure an FPGA using macro markers 有权
标题翻译：使用宏标记安全配置FPGA的方法
公开(公告)号：US06301695B1
公开(公告)日：2001-10-09
申请号：US09231912
申请日：1999-01-14
申请人： James L. Burnham , Gary R. Lawman
发明人： James L. Burnham , Gary R. Lawman
IPC分类号： G06F1750
CPC分类号： G06F21/76 , G06F17/5054
摘要： A method is provided for securely configuring an FPGA with macros. Specifically, if an end user desires to use a macro from a macro vendor, the end user creates a marked design file containing a macro marker rather than the actual macro. The marked design file is converted into configuration data by a macro manager. Specifically, the macro manager obtains the macro from the macro vendor and replaces the macro marker with the macro prior to converting the design file into configuration data. The macro manager provides the configuration data to the end user. Because only the macro manager has access to the macro, the possibility of unlicensed use of the macro is diminished.
摘要翻译：提供了一种用于使用宏安全配置FPGA的方法。具体来说，如果最终用户希望使用来自宏供应商的宏，则最终用户创建包含宏标记而不是实际宏的标记设计文件。标记的设计文件由宏管理器转换为配置数据。具体来说，宏管理器从宏供应商处获取宏，并在将设计文件转换成配置数据之前用宏替换宏标记。宏管理器向最终用户提供配置数据。由于只有宏管理器可以访问宏，所以无法使用宏的可能性就会减弱。

9. 发明授权

US6049222A Configuring an FPGA using embedded memory 失效
标题翻译：使用嵌入式内存配置FPGA
公开(公告)号：US6049222A
公开(公告)日：2000-04-11
申请号：US1036
申请日：1997-12-30
申请人： Gary R. Lawman
发明人： Gary R. Lawman
IPC分类号： G06F15/78 , G06F17/50 , H03K19/173
CPC分类号： G06F17/5054 , G06F15/7867
摘要： An FPGA includes an embedded non-volatile memory coupled to a configuration access port. The configuration access port allows the non-volatile memory to program the configuration memory of the FPGA. On power-on or reset, the non-volatile memory configures a first portion of the FPGA using configuration data stored in the non-volatile memory. Other portions of the FPGA can also be configured using the embedded non-volatile memory. Alternatively, an external configuration device can configure the other portions of the FPGA through a configuration port. Further, either the embedded non-volatile memory or the external configuration device can reconfigure the first portion of the FPGA.
摘要翻译： FPGA包括耦合到配置访问端口的嵌入式非易失性存储器。配置访问端口允许非易失性存储器编程FPGA的配置存储器。在上电或复位时，非易失性存储器使用存储在非易失性存储器中的配置数据来配置FPGA的第一部分。也可以使用嵌入式非易失性存储器来配置FPGA的其他部分。或者，外部配置设备可以通过配置端口配置FPGA的其他部分。此外，嵌入式非易失性存储器或外部配置设备可以重新配置FPGA的第一部分。

10. 发明授权

US5946478A Method for generating a secure macro element of a design for a programmable IC 失效
标题翻译：用于生成用于可编程IC的设计的安全宏元件的方法
公开(公告)号：US5946478A
公开(公告)日：1999-08-31
申请号：US857439
申请日：1997-05-16
申请人： Gary R. Lawman
发明人： Gary R. Lawman
IPC分类号： G06F17/50 , G06F21/00
CPC分类号： G06F21/76 , G06F17/5054 , G06F2217/66
摘要： A method of generating and using a secure macro element for configuring programmable ICs is provided. The method provides a bitstream to a user, rather than providing a user-editable macro. Compilation software is provided to the user that combines the data from a "macro bitstream" (the bitstream comprising the macro data description) and the data from the user's own circuits to create the complete bitstream. The compilation software reserves the relevant portions of the complete bitstream for the macro, and does not assign user circuits to the areas controlled by those portions of the bitstream. In one embodiment of the invention, the user specifies a physical location on the programmable IC for the macro, so the macro data is optionally placed in a different location in the complete bitstream than in the macro bitstream. In another embodiment, the macro bitstream and the complete bitstream represent the same programmable IC architecture, but not the same device, so they are of similar formats but different lengths.
摘要翻译：提供了一种生成和使用用于配置可编程IC的安全宏元素的方法。该方法向用户提供比特流，而不是提供用户可编辑的宏。提供了将来自“宏比特流”（包括宏数据描述的比特流）和来自用户自身电路的数据的数据组合的用户的编译软件，以创建完整的比特流。编译软件保留宏的完整比特流的相关部分，并且不将用户电路分配给由比特流的这些部分控制的区域。在本发明的一个实施例中，用户指定用于宏的可编程IC上的物理位置，因此宏数据可选地位于完整比特流中的比在宏比特流中的不同位置。在另一个实施例中，宏比特流和完整比特流表示相同的可编程IC架构，但不是相同的设备，因此它们具有相似的格式但不同的长度。

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