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    • 8. 发明授权
    • Debugger recovery on exit from low power mode
    • 从低功耗模式退出时调试器恢复
    • US08601315B2
    • 2013-12-03
    • US12917470
    • 2010-11-01
    • Robert EhrlichGeorge BakerAlan Carlin
    • Robert EhrlichGeorge BakerAlan Carlin
    • G06F11/00
    • G06F11/3648G06F1/3203G06F11/3656
    • A device is configured with components to enable debugging of the device's entry into and exit from a low power mode. The device includes: core logic, debug components, and a power management module (PMM). When the device exits a low power mode in which the states of the debug components are lost, the PMM prevents the core logic from resuming processing operations until the debug components have been re-configured to their prior states. The PMM either holds the core logic in reset or alternatively withholds power to the core logic. Reconfiguration of the debug components is initiated by a connected debugger, which can set one or more control and status (CS) register values within the device. The CS register values determine when the PMM prevents the core logic processing from resuming and when the PMM enables core logic processing to resume following the device's return from low power mode.
    • 设备配置有组件,以使设备进入和退出低功耗模式的调试。 该设备包括:核心逻辑,调试组件和电源管理模块(PMM)。 当设备退出调试组件的状态丢失的低功耗模式时,PMM将防止核心逻辑恢复处理操作,直到调试组件重新配置为其先前状态。 PMM或者将核心逻辑保持在复位状态,或者替代地保留核心逻辑的电源。 调试组件的重新配置由连接的调试器启动,可以在设备内设置一个或多个控制和状态(CS)寄存器值。 CS寄存器值确定PMM何时防止核心逻辑处理恢复,当PMM使得核心逻辑处理能够在设备从低功耗模式返回后恢复。