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    • 4. 发明申请
    • Method and apparatus for memory self testing
    • 记忆自检的方法和装置
    • US20060200713A1
    • 2006-09-07
    • US11072626
    • 2005-03-07
    • Richard SlobodnikFrank Frederick
    • Richard SlobodnikFrank Frederick
    • G11C29/00
    • G11C29/18G11C2029/1806G11C2029/3602
    • A memory self-test system is provided comprising a self-test controller operable in self-test mode to generate a sequence of generated memory addresses for performing memory access operations associated with the memory test algorithm having an associated memory cell physical access pattern. A programmable re-mapper is operable to re-map the sequence of generated memory addresses derived from the self-test instruction to a sequence of re-mapped memory addresses. The programmable re-mapper performs this re-mapping in response to programmable mapping selection data. The re-mapping of the generated memory addresses to re-mapped memory addresses ensures that the memory cell accesses performed during execution of the memory self-test are consistent with the associated memory cell physical access pattern regardless of the particular implementation of the memory array.
    • 提供了一种存储器自检系统,其包括在自检模式下可操作的自检程序,以生成一系列生成的存储器地址,以执行与具有相关联的存储单元物理访问模式的存储器测试算法相关联的存储器访问操作。 可编程重新映射器可操作以将从自测试指令导出的生成的存储器地址的序列重新映射到重新映射的存储器地址的序列。 可编程重新映射器响应于可编程映射选择数据执行该重映射。 将生成的存储器地址重新映射到重新映射的存储器地址确保在执行存储器自检期间执行的存储器单元访问与相关联的存储器单元物理访问模式一致,而不管存储器阵列的特定实现。
    • 8. 发明申请
    • Integrated circuit and method for testing memory on the integrated circuit
    • 用于集成电路测试存储器的集成电路和方法
    • US20060212764A1
    • 2006-09-21
    • US11076020
    • 2005-03-10
    • Richard SlobodnikPaul HughesFrank FrederickBrandon Backlund
    • Richard SlobodnikPaul HughesFrank FrederickBrandon Backlund
    • G11C29/00
    • G11C29/16G11C29/26G11C29/48G11C2029/0401G11C2029/3602
    • An integrated circuit and method for testing memory on that integrated circuit are provided. The integrated circuit comprises processing logic operable to perform data processing operations on data, and a number of memory units operable to store data for access by the processing logic. A memory test controller is also provided which is operable to execute test events in order to seek to detect any memory defects in the number of memory units. The memory test controller comprises a storage operable to store event defining information for each of a plurality of test events forming a sequence of test events to be executed, and an interface which, during a single programming operation, receives the event defining information for each of the plurality of test events and causes that event defining information to be stored in the storage. Event processing logic within the memory test controller is then operable, following the single programming operation, to execute the sequence of test events. This provides an efficient technique for enabling a sequence of test events to be programmed at run time.
    • 提供了一种用于测试该集成电路上的存储器的集成电路和方法。 集成电路包括可操作以对数据执行数据处理操作的处理逻辑,以及可操作以存储用于由处理逻辑进行访问的数据的多个存储单元。 还提供了一种存储器测试控制器,其可操作以执行测试事件,以便寻求检测存储器单元数量中的任何存储器缺陷。 存储器测试控制器包括可操作以存储形成要执行的测试事件序列的多个测试事件中的每一个的事件定义信息的存储器,以及在单个编程操作期间接收每个测试事件的事件定义信息的接口 所述多个测试事件并且使所述事件定义要存储在所述存储器中的信息。 然后,在单个编程操作之后,存储器测试控制器内的事件处理逻辑可以执行测试事件的顺序。 这提供了一种有效的技术,可以在运行时对一系列测试事件进行编程。
    • 10. 发明授权
    • Scan clock circuit and method therefor
    • 扫描时钟电路及其方法
    • US06877123B2
    • 2005-04-05
    • US10025291
    • 2001-12-19
    • Thomas K. JohnstonFrank Frederick
    • Thomas K. JohnstonFrank Frederick
    • G01R31/317G01R31/3185G01R31/28
    • G01R31/318552G01R31/31727
    • Embodiments of the present invention relate generally to scan clock waveform generation. One embodiment utilizes global and local circular shift registers to provide a series of shift/capture pulses at a manageable frequency for the tester and launch pulses that are phase shifted in order to provide for at-speed testing. Therefore, scan test patterns may be shifted in or out of state elements at lower frequencies as compared to the normal operating frequency of the integrated circuit being tested, while still allowing for at-speed testing. An alternate embodiment utilizes a circular shift register in combination with static storage devices and waveform generators to provide the shift/capture pulses and launch pulses. Embodiments of the present invention also allow for clock inversion where the clock and clock bar signals are dependent during normal mode and independent during scan test mode.
    • 本发明的实施例一般涉及扫描时钟波形生成。 一个实施例使用全局和局部圆形移位寄存器来提供针对测试器的可管理频率的一系列移位/捕获脉冲和相移的启动脉冲,以便提供高速测试。 因此,与待测集成电路的正常工作频率相比,扫描测试图案可以以更低的频率移入或移出状态元件,同时仍允许进行高速测试。 替代实施例利用与静态存储设备和波形发生器组合的循环移位寄存器来提供移位/捕获脉冲和启动脉冲。 本发明的实施例还允许时钟反转,其中时钟和时钟条信号在正常模式期间是依赖的,并且在扫描测试模式期间是独立的。