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1. 发明授权

US6008678A Three-phase master-slave flip-flop 失效
标题翻译：三相主从触发器
公开(公告)号：US6008678A
公开(公告)日：1999-12-28
申请号：US844963
申请日：1997-04-23
申请人： Frank E. Barber
发明人： Frank E. Barber
IPC分类号： H03K3/037 , H03K3/3562 , H03K3/289 , H03K3/356
CPC分类号： H03K3/35625 , H03K3/0375
摘要： A master-slave flip-flop has two switches that control the flow of data into and through the master and slave stages. The switches are controlled by a three-phase clock signal that is designed to address the problem of data shoot-through. Implementations of the flip-flop rely on weak feedback techniques that allow the flip-flops to be implemented using weak keeper devices in the feedback paths of the master and slave stages and without switches in those feedback paths. The flip-flop enables fast and reliable flip-flops to be implemented with minimal layout area and power consumption.
摘要翻译：主从触发器有两个开关，用于控制数据流入和通过主站和从站的数据流。开关由三相时钟信号控制，旨在解决数据直通问题。触发器的实现依赖于弱反馈技术，这些技术允许在主级和从级的反馈路径中使用弱保持器器件来实现触发器，并且在那些反馈路径中不使用开关。触发器使得能够以最小的布局面积和功耗实现快速可靠的触发器。

2. 发明授权

US5380290A Body access device 失效
标题翻译：身体进入装置
公开(公告)号：US5380290A
公开(公告)日：1995-01-10
申请号：US870140
申请日：1992-04-16
申请人： Joshua Makower , Earl H. Slee , Naomi C. Chesler , William J. Gorman , Frank E. Barber
发明人： Joshua Makower , Earl H. Slee , Naomi C. Chesler , William J. Gorman , Frank E. Barber
IPC分类号： A61M25/06 , A61M5/178
CPC分类号： A61M25/065 , A61M25/06 , A61M25/0662
摘要： A device for providing access to a living body. The device, in one embodiment, includes a slotted needle dimensioned and configured to receive, in fluid tight engagement, a catheter or a guidewire introduced into the needle through the slot. The device, in another embodiment, includes a sharpened, slotted first tube, a second tube piercable by the first tube for receipt therein of at least a potion of both the first tube and the slot, and an elongated element passing into the second tube, through the slot and into the first tube. The device might further include a third tube slidably positioned around the second tube.
摘要翻译：用于提供对生物体的通路的装置。在一个实施例中，该装置包括定尺寸和构造为以流体密封接合的方式接收通过狭槽引入到针中的导管或导丝的开槽针。在另一个实施例中，该装置包括一个锋利的开槽的第一管，由第一管可穿透的第二管，用于在其中容纳至少一个第一管和槽的两个部分，以及一个伸入第二管的细长元件，通过插槽并进入第一个管。该装置还可以包括围绕第二管可滑动定位的第三管。

3. 发明授权

US4849751A CMOS Integrated circuit digital crossbar switching arrangement 失效
标题翻译： CMOS集成电路数字交叉开关布置
公开(公告)号：US4849751A
公开(公告)日：1989-07-18
申请号：US58968
申请日：1987-06-08
申请人： Frank E. Barber , Masakazu Shoji
发明人： Frank E. Barber , Masakazu Shoji
IPC分类号： H01L21/8238 , H01L27/092 , H03K17/00 , H03K19/00 , H03K19/003 , H03K19/0175 , H03K19/173
CPC分类号： H03K19/00323 , H03K19/1737
摘要： A CMOS logic circuit, such as a crossbar digital switch, multistage multiplexer logic tree in a two-column compact folded layout of two columns, each having a width equal to a single stage of the tree, in order to minimize wiring delays and hence signal skew. Each stage of the tree, except for the first, includes a symmetrized two-input CMOS NAND gate followed in cascade by a symmetrized CMOS INVERTER gate, to minimize signal skew otherwise caused by the difference between pull-up and pull-down gate delays of CMOS gates and the skew otherwise caused by variations in semiconductor manufacturing processing conditions and variations in ambient operating conditions (temperature and power supply voltages). Also, a detailed delay balancing scheme separately for pull-up and pull-down gate delays is implemented along a pair of signal paths for generating each output signal and its simultaneous complement without relative skew between them. In this way a single-chip 64 input.times.17 output CMOS digital crossbar switch can be made to operate with date rates as high as 300 megabits per second.

4. 发明授权

US4620118A Dual port access circuit with automatic asynchronous contention resolving capability 失效
标题翻译：具有自动异步争用解决能力的双端口访问电路
公开(公告)号：US4620118A
公开(公告)日：1986-10-28
申请号：US432289
申请日：1982-10-01
申请人： Frank E. Barber
发明人： Frank E. Barber
IPC分类号： G06F15/167 , G06F12/00 , G06F13/14 , G06F13/18 , G11C11/41 , H03K17/28 , H03K5/26
CPC分类号： G06F13/14 , G06F13/18
摘要： Two microprocessors, which may be operating asynchronously, share a random access memory (RAM) array; that is, at any one moment of time, either microprocessor can seek access to the RAM but only one of them can actually gain access at a time. Priority of access to the RAM is controlled by a dual port contention-resolving access circuit which enables such access alternately to the two microprocessors when both are seeking (overlapping) access, subject to the stipulation when neither microprocessor is accessing the RAM that the very next access will be allocated by the circuit on a first-come first-served basis, and will be allocated to a preselected one of the microprocessors if both microprocessors will commence to seek access precisely at the same time.
摘要翻译：可以异步操作的两个微处理器共享随机存取存储器（RAM）阵列; 也就是说，在任何一个时刻，任何一个微处理器都可以访问RAM，但是其中只有一个实际上可以一次访问。访问RAM的优先级由双端口争用解决访问电路控制，当两者都正在寻找（重叠）访问时，这两个微处理器可以交替访问两个微处理器，在两个微处理器都没有访问RAM的情况下访问将按照先到先得的原则由电路分配，并且如果两个微处理器将在同一时间开始寻求访问，则将被分配给预选的一个微处理器。

5. 发明授权

US4627030A Dual port memory word size expansion technique 失效
标题翻译：双端口存储字大小扩展技术
公开(公告)号：US4627030A
公开(公告)日：1986-12-02
申请号：US698076
申请日：1985-02-04
申请人： Frank E. Barber
发明人： Frank E. Barber
IPC分类号： G11C7/00 , G06F12/16 , G11C7/10 , G11C8/16 , G11C11/34 , G11C11/41
CPC分类号： G11C8/16 , G11C7/1006 , G11C7/1075
摘要： An improved technique for word size expansion using dual port random access memories (DPRs) allows multiple integrated circuit chips to be used without introducing erroneous data. A master chip provides a signal derived from its conflict resolution circuitry to one or more slave chips. This prevents one or more chips in a word size expansion arrangement from selecting opposite ports when two access requests arrive simultaneously. An optional address latch input to the chips allows the retention of the same address hold time parameter for the expanded word as for a single DPR chip.
摘要翻译：使用双端口随机存取存储器（DPR）的改进的字体扩展技术允许使用多个集成电路芯片而不引入错误的数据。主芯片提供从其冲突解决电路得到的信号到一个或多个从芯片。这可以防止当两个访问请求同时到达时，字大小扩展排列中的一个或多个芯片选择相对的端口。输入到芯片的可选地址锁存器允许为单个DPR芯片保留与扩展字相同的地址保持时间参数。

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