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    • 3. 发明申请
    • SENSOR, A SENSOR ARRAY, AND A METHOD OF OPERATING A SENSOR
    • 传感器,传感器阵列和操作传感器的方法
    • US20100221846A1
    • 2010-09-02
    • US12682608
    • 2008-10-07
    • Franciscus Widdershoven
    • Franciscus Widdershoven
    • G01N33/563G01N33/50G01N27/00
    • G01N33/5438C12Q1/6825Y10T436/143333
    • In an example embodiment, there is a sensor for detecting particles. The sensor comprises an electrode, a sensor active region covering the electrode and the sensor active region is sensitive-for the particles. A first switch element is operable to bring the electrode to a first electric potential when the first switch element is closed, and a second switch element is operable to bring the electrode to a second electric potential when the second switch element is closed. A detector is adapted to detect the particles based on a change of the electric properties of the sensor in an operation mode in which the electrode is brought to the first electric potential and an operation mode in which the electrode is brought to the second electric potential.
    • 在示例性实施例中,存在用于检测颗粒的传感器。 传感器包括电极,覆盖电极的传感器有源区域和传感器有源区域对于颗粒是敏感的。 第一开关元件可操作以在第一开关元件闭合时使电极达到第一电位,并且当第二开关元件闭合时第二开关元件可操作以使电极达到第二电位。 检测器适于基于在将电极带到第一电位的操作模式中的传感器的电特性的变化和使电极达到第二电位的操作模式来检测颗粒。
    • 8. 发明申请
    • Self-aligned 2-bit
    • 自对准2位“双聚CMP”闪存单元
    • US20060163642A1
    • 2006-07-27
    • US10532292
    • 2002-08-18
    • Franciscus WiddershovenMichiel Van Duuren
    • Franciscus WiddershovenMichiel Van Duuren
    • H01L29/788
    • G11C16/0458H01L27/115H01L27/11521
    • Fabrication of a memory cell, the cell including a first floating gate stack (A), a second floating gate stack (B) and an intermediate access gate (AG), the floating gate stacks (A, B) including a first gate oxide (4), a floating gate (FG), a control gate (CG; CGl, CGu), an interpoly dielectric layer (8), a capping layer (6) and side-wall spacers (10), the cell further including source and drain contacts (22), wherein the fabrication includes: defining the floating gate stacks in the same processing steps to have equal heights; depositing over the floating gate stacks a poly-Si layer (12) with a larger thickness than the floating gate stacks' height; planarizing the poly-Si layer (12); defining the intermediate access gate (AG) in the planarized poly-Si layer (14) by means of an access gate masking step over the poly-Si layer between the floating gate stacks and a poly-Si etching step.
    • 存储单元的制造,该单元包括第一浮栅堆叠(A),第二浮栅堆叠(B)和中间存取栅极(AG),所述浮栅叠层(A,B)包括第一栅氧化层 4),浮动栅极(FG),控制栅极(CG; CG1,CGu),多晶硅间介电层(8),封盖层(6)和侧壁间隔物(10) 漏极触点(22),其中所述制造包括:在相同的处理步骤中限定所述浮栅堆叠以具有相同的高度; 在浮栅上沉积堆叠具有比浮栅堆叠高度更大的厚度的多晶硅层(12); 平面化多晶硅层(12); 通过在浮栅堆叠之间的多晶硅层和多晶硅蚀刻步骤之间的存取栅掩模步骤,在平坦化的多晶硅层(14)中限定中间栅极(AG)。