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1. 发明申请

US20130073761A1 NETWORK COMMUNICATIONS CIRCUIT, SYSTEM AND METHOD 有权
标题翻译：网络通信电路，系统和方法
公开(公告)号：US20130073761A1
公开(公告)日：2013-03-21
申请号：US13234798
申请日：2011-09-16
申请人： Peter Gustaaf Nierop , Clemens Gerhardus Johannes de Haas , Rainer Evers , Franciscus Johannes Klosters
发明人： Peter Gustaaf Nierop , Clemens Gerhardus Johannes de Haas , Rainer Evers , Franciscus Johannes Klosters
IPC分类号： G06F13/40 , G06F13/00
CPC分类号： H04L12/40045 , H04L2012/40234
摘要： Various exemplary aspects are directed to apparatuses and methods involving switches communicatively-coupled on a bus where one or more of the switches operate to block signals from passing through the switch in a first mode, and to pass signals through the switch in a second mode. A logic circuit is responsive to addressing information received in the first mode, by storing and configuring the apparatus with the address information. The logic circuit ignores address information received in the second mode (e.g., does not reconfigure the apparatus with address information received in the second mode).
摘要翻译：各种示例性方面针对涉及通信耦合在总线上的开关的装置和方法，其中一个或多个开关操作以在第一模式中阻止信号通过开关，并且以第二模式传递信号通过开关。逻辑电路响应于以第一模式接收的寻址信息，通过存储和配置具有地址信息的设备。逻辑电路忽略在第二模式中接收的地址信息（例如，不重新配置在第二模式中接收到的地址信息的装置）。

2. 发明授权

US08266346B2 Data processing apparatus that processes incoming bits 有权
标题翻译：处理传入位的数据处理装置
公开(公告)号：US08266346B2
公开(公告)日：2012-09-11
申请号：US10531399
申请日：2003-09-19
申请人： Franciscus Johannes Klosters , Patrick Willem Hubert Heuts , Joris Rudolf Beverloo , Hendrik Bernard Heule
发明人： Franciscus Johannes Klosters , Patrick Willem Hubert Heuts , Joris Rudolf Beverloo , Hendrik Bernard Heule
IPC分类号： G06F3/00
CPC分类号： H04L7/046 , H04L7/06
摘要： A data processing apparatus receives a communication signal that contains temporally successive bits. A programmable processor circuit executes a plurality of series of programmed instructions for operations such as parity checking, each at a time of reception of a respective one of the bits. The processor circuit suspends operation each time after executing a respective one of the series of instructions. A synchronization circuit triggers execution of respective ones of the series, each time at the time of reception of the respective one of the bits, and, except for a last one of the series, prior to reception of one or more later bits that contribute to the data word.
摘要翻译：数据处理装置接收包含时间上连续的比特的通信信号。可编程处理器电路在接收到相应的一个位时，执行多个编程指令，用于诸如奇偶校验的操作。处理器电路在执行一系列指令中的相应一个之后每次暂停操作。同步电路在接收到一个或多个稍后的位之前，每次在接收到相应的一个位时每次触发该系列中的相应的一个，并且除了该系列的最后一个之外数据字。

3. 发明授权

US08935450B2 Network communications circuit, system and method 有权
标题翻译：网络通信电路，系统及方法
公开(公告)号：US08935450B2
公开(公告)日：2015-01-13
申请号：US13234798
申请日：2011-09-16
申请人： Pieter Gustaaf Nierop , Clemens Gerhardus Johannes de Haas , Rainer Evers , Franciscus Johannes Klosters
发明人： Pieter Gustaaf Nierop , Clemens Gerhardus Johannes de Haas , Rainer Evers , Franciscus Johannes Klosters
IPC分类号： G06F3/00 , G06F13/00 , H04L12/40
CPC分类号： H04L12/40045 , H04L2012/40234
摘要： Various exemplary aspects are directed to apparatuses and methods involving switches communicatively-coupled on a bus where one or more of the switches operate to block signals from passing through the switch in a first mode, and to pass signals through the switch in a second mode. A logic circuit is responsive to addressing information received in the first mode, by storing and configuring the apparatus with the address information. The logic circuit ignores address information received in the second mode (e.g., does not reconfigure the apparatus with address information received in the second mode).
摘要翻译：各种示例性方面针对涉及通信耦合在总线上的开关的装置和方法，其中一个或多个开关操作以在第一模式中阻止信号通过开关，并且以第二模式传递信号通过开关。逻辑电路响应于以第一模式接收的寻址信息，通过存储和配置具有地址信息的设备。逻辑电路忽略在第二模式中接收的地址信息（例如，不重新配置在第二模式中接收的地址信息的装置）。

4. 发明授权

US07620135B2 Data processing apparatus that identifies a communication clock frequency 失效
标题翻译：识别通信时钟频率的数据处理装置
公开(公告)号：US07620135B2
公开(公告)日：2009-11-17
申请号：US10531397
申请日：2003-08-13
申请人： Franciscus Johannes Klosters , Patrick Willem Hubert Heuts , Joris Rudolf Beverloo , Hendrik Bernard Heule
发明人： Franciscus Johannes Klosters , Patrick Willem Hubert Heuts , Joris Rudolf Beverloo , Hendrik Bernard Heule
IPC分类号： H04L7/00
CPC分类号： H04L25/0262 , H04L7/044 , H04L7/046
摘要： A data processing apparatus receives a message containing a sync break interval with a unique bit pattern and a sync field interval identified by the sync break interval. A timing property of the sync field interval specifies the length of bit periods of the message. A clock source circuit supplies a sampling clock signal to define time points for sampling bits from the message. The clock source circuit adapts a frequency of the sampling clock signal to the timing property of the sync field interval. The clock source circuit searches for potential sync break intervals that match the unique bit pattern for a range of bit period values and verifies for each potential sync break interval whether the sync field interval identified by that potential sync break interval specifies a bit period with a duration so that the sync break interval matches the unique pattern for the specified bit period, as a condition prior to supplying the sampling clock signal at the adapted frequency specified by the sync field interval identified by the potential sync break interval. Supply of sampling clock signals is preferably suppressed after an end of a preceding message until said condition is met.
摘要翻译：数据处理装置接收包含具有由同步中断间隔识别的唯一位模式和同步字段间隔的同步中断间隔的消息。同步字段间隔的定时属性指定消息的位周期的长度。时钟源电路提供采样时钟信号以定义来自消息的采样位的时间点。时钟源电路使采样时钟信号的频率适应于同步信号间隔的定时特性。时钟源电路搜索与位周期值范围的唯一位模式匹配的潜在同步中断间隔，并验证每个潜在同步中断间隔，无论由该潜在同步中断间隔识别的同步字段间隔是否指定持续时间的位周期使得同步中断间隔与指定位周期的唯一模式匹配，作为在由潜在同步中断间隔识别的同步字段间隔指定的适配频率提供采样时钟信号之前的状态。优选地，在先前消息结束之后抑制采样时钟信号的提供直到满足所述条件。

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