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1. 发明授权

US06943098B2 Method of forming semiconductor device with non-conformal liner layer that is thinner on sidewall surfaces 失效
标题翻译：用侧壁表面较薄的非保形衬层形成半导体器件的方法
公开(公告)号：US06943098B2
公开(公告)日：2005-09-13
申请号：US10605326
申请日：2003-09-23
申请人： Fang-Yu Yeh , Chun-Che Chen
发明人： Fang-Yu Yeh , Chun-Che Chen
IPC分类号： H01L21/31 , H01L21/3205 , H01L21/336 , H01L21/469 , H01L21/4763 , H01L21/477 , H01L21/60 , H01L21/768
CPC分类号： H01L21/76897 , H01L21/76838 , H01L29/6656
摘要： A method of forming a contact opening is provided. First, a substrate having a plurality of conductive structures formed thereon is provided. An ion implantation is performed. Thereafter, a thermal treatment is carried out to form a liner layer on the sidewall of the conductive structure and the exposed substrate. The liner layer on the sidewall of the conductive structure has a thickness smaller than the liner layer on the substrate surface. A spacer is formed on each side of the conductive structure and then an insulation layer is formed over the substrate. The insulation layer is patterned to form a contact opening between two neighboring conductive structures. Since the liner layer on the sidewall of the conductive structures is already quite thin, there is no need to reduce thickness through an etching operation and uniformity of the liner layer on the substrate can be ensured.
摘要翻译：提供一种形成接触开口的方法。首先，提供其上形成有多个导电结构的基板。进行离子注入。此后，进行热处理以在导电结构的侧壁和暴露的基板上形成衬垫层。导电结构的侧壁上的衬垫层的厚度小于衬底表面上的衬垫层。在导电结构的每一侧上形成间隔物，然后在衬底上形成绝缘层。图案化绝缘层以在两个相邻导电结构之间形成接触开口。由于导电结构的侧壁上的衬垫层已经相当薄，所以不需要通过蚀刻操作来减小厚度，并且可以确保衬底上的衬垫层的均匀性。

2. 发明申请

US20090008781A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20090008781A1
公开(公告)日：2009-01-08
申请号：US12211068
申请日：2008-09-15
申请人： Bai-rou Ni , Fang-Yu Yeh , Yueh-Chuan Lee
发明人： Bai-rou Ni , Fang-Yu Yeh , Yueh-Chuan Lee
IPC分类号： H01L29/51
CPC分类号： H01L21/28061 , H01L21/823443 , H01L21/82345 , H01L21/823835 , H01L21/823842 , H01L29/51 , H01L29/66583
摘要： A semiconductor device structure includes a substrate, a first conductive layer over the substrate, a second conductive layer between the first conductive layer and the substrate and extending over the sidewalls of the first conductive layer, a dielectric layer between the second conductive layer and the substrate, a cap layer over the first conductive layer and the second conductive layer, and a liner layer on the sidewalls of the second conductive layer.
摘要翻译：半导体器件结构包括衬底，在衬底上的第一导电层，在第一导电层和衬底之间并在第一导电层的侧壁上延伸的第二导电层，在第二导电层和衬底之间的介电层，在第一导电层和第二导电层之上的覆盖层，以及在第二导电层的侧壁上的衬层。

3. 发明申请

US20060017165A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20060017165A1
公开(公告)日：2006-01-26
申请号：US11163121
申请日：2005-10-05
申请人： Bai-rou Ni , Fang-Yu Yeh , Yueh-Chuan Lee
发明人： Bai-rou Ni , Fang-Yu Yeh , Yueh-Chuan Lee
IPC分类号： H01L21/4763 , H01L21/44 , H01L23/48
CPC分类号： H01L21/28061 , H01L21/823443 , H01L21/82345 , H01L21/823835 , H01L21/823842 , H01L29/51 , H01L29/66583
摘要： A method of manufacturing a semiconductor device comprises the steps as follow. After forming an insulating layer with opening therein over a substrate, a polysilicon layer that partially fills the opening is formed over the substrate and then a refractory metal silicide layer that completely fills the opening is formed over the substrate. Thereafter, the polysilicon layer and the refractory metal silicide layer outside the opening are removed to expose the insulating layer. A portion of the polysilicon layer and the refractory metal silicide layer are etched back so that the surface of the polysilicon layer and the refractory metal silicide layer are below the surface of the insulating layer. After forming a cap layer over the polysilicon layer and the refractory metal silicide layer, the insulating layer is removed and then a liner layer is formed on the sidewalls of the polysilicon layer.
摘要翻译：制造半导体器件的方法包括以下步骤。在衬底上形成开口的绝缘层之后，在衬底上形成部分填充开口的多晶硅层，然后在衬底上形成完全填充开口的难熔金属硅化物层。此后，去除开口外部的多晶硅层和难熔金属硅化物层，露出绝缘层。多晶硅层和难熔金属硅化物层的一部分被回蚀刻，使得多晶硅层和难熔金属硅化物层的表面在绝缘层的表面之下。在多晶硅层和难熔金属硅化物层上形成覆盖层之后，去除绝缘层，然后在多晶硅层的侧壁上形成衬层。

4. 发明授权

US06929989B2 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US06929989B2
公开(公告)日：2005-08-16
申请号：US10604509
申请日：2003-07-28
申请人： Fang-Yu Yeh , Chi Lin , Chuang-Hsiang Chen
发明人： Fang-Yu Yeh , Chi Lin , Chuang-Hsiang Chen
IPC分类号： H01L21/336 , H01L29/10 , H01L29/78 , H01L21/8234
CPC分类号： H01L29/66621 , H01L29/1033 , H01L29/7834
摘要： A method of manufacturing a semiconductor device is provided. First, a well region is formed in a substrate and then a mask layer is formed over the substrate. The mask layer and the substrate are patterned to form a first opening in the substrate. Thereafter, a threshold voltage adjustment process is performed. A gate dielectric layer, a first conductive layer and a second conductive layer are sequentially formed inside the first opening. The second conductive layer completely fills the first opening. A portion of the first conductive layer and the second conductive layer are removed so that the upper surface of the first conductive layer and the second conductive layer is slightly below the upper surface of the substrate and hence forms a second opening. A cap layer is formed in second opening and then the mask layer is removed. A source/drain region is formed in the substrate on each side of the first conductive layer. An inter-layer dielectric layer is formed over the substrate. Finally, using the cap layer as a self-aligned mask, a contact opening is formed in the inter-layer dielectric layer.
摘要翻译：提供一种制造半导体器件的方法。首先，在衬底中形成阱区，然后在衬底上形成掩模层。将掩模层和基板图案化以在基板中形成第一开口。此后，执行阈值电压调整处理。在第一开口内依次形成栅介电层，第一导电层和第二导电层。第二导电层完全填充第一开口。去除第一导电层和第二导电层的一部分，使得第一导电层和第二导电层的上表面略低于衬底的上表面，因此形成第二开口。在第二开口中形成盖层，然后去除掩模层。源极/漏极区域形成在第一导电层的每一侧上的衬底中。在衬底上形成层间电介质层。最后，使用盖层作为自对准掩模，在层间电介质层中形成接触开口。

5. 发明授权

US06559044B1 Method for forming contacts 有权
标题翻译：形成接触的方法
公开(公告)号：US06559044B1
公开(公告)日：2003-05-06
申请号：US10237799
申请日：2002-09-10
申请人： Chun-Che Chen , Fang-Yu Yeh , Han-Chih Lin , Chin-Sheng Chen
发明人： Chun-Che Chen , Fang-Yu Yeh , Han-Chih Lin , Chin-Sheng Chen
IPC分类号： H01L214763
CPC分类号： H01L21/76897 , H01L21/76802
摘要： A method for forming contacts in a semiconductor device including a plurality of active devices formed over a substrate that includes depositing a first layer of dielectric material over the substrate and plurality of active devices, forming a first opening in the first layer of dielectric material, depositing a second layer of dielectric material over the first layer of dielectric material and in the first opening, providing a mask over the second layer of dielectric material, wherein the mask material is distinguishable over silicon oxides, and forming a second opening and a third opening in the second layer of dielectric material, wherein the second opening is aligned with the first opening and exposes a first silicide of a first active device, and the third opening exposes one of diffused regions of a second active device.
摘要翻译：一种用于在半导体器件中形成接触的方法，所述半导体器件包括形成在衬底上的多个有源器件，所述有源器件包括在所述衬底上沉积介电材料的第一层和多个有源器件，在所述第一介电材料层中形成第一开口，在所述第一介电材料层上并且在所述第一开口中的第二介电材料层，在所述第二介电材料层上提供掩模，其中所述掩模材料可以在硅氧化物上区分，并形成第二开口和第三开口所述第二介电材料层，其中所述第二开口与所述第一开口对准并且暴露第一有源器件的第一硅化物，并且所述第三开口暴露第二有源器件的扩散区域中的一个。

6. 发明授权

US07049245B2 Two-step GC etch for GC profile and process window improvement 有权
标题翻译：两步GC蚀刻GC图和工艺窗口改进
公开(公告)号：US07049245B2
公开(公告)日：2006-05-23
申请号：US10660821
申请日：2003-09-12
申请人： Fang-Yu Yeh , Chi Lin , Chia-Yao Chen
发明人： Fang-Yu Yeh , Chi Lin , Chia-Yao Chen
IPC分类号： H01L21/302
CPC分类号： H01L21/28061 , H01L21/32137 , H01L21/32139
摘要： A method for manufacturing a semiconductor device that comprises defining a semiconductor substrate, forming a gate oxide on the semiconductor substrate, forming a polycrystalline silicon layer over the gate oxide, forming a tungsten silicide layer over the polycrystalline silicon layer; providing a mask over the tungsten silicide layer, defining the mask to expose at least one portion of the tungsten silicide layer, etching the exposed tungsten silicide layer with a first etchant, wherein some tungsten silicide layer remains, etching the remaining tungsten silicide layer with a second etchant to expose at least one portion of the polycrystalline silicon layer, annealing the tungsten silicide layer, etching the exposed polycrystalline silicon layer, and oxidizing sidewalls of the tungsten silicide layer and the polycrystalline silicon layer.
摘要翻译：一种制造半导体器件的方法，包括限定半导体衬底，在半导体衬底上形成栅极氧化物，在栅极氧化物上形成多晶硅层，在多晶硅层上形成硅化钨层; 在所述硅化钨层上提供掩模，限定所述掩模以暴露所述硅化钨层的至少一部分，用第一蚀刻剂蚀刻所述暴露的硅化钨层，其中保留一些硅化钨层，用第二蚀刻剂以暴露多晶硅层的至少一部分，退火硅化钨层，蚀刻暴露的多晶硅层，以及氧化硅化钨层和多晶硅层的侧壁。

7. 发明申请

US20050202625A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20050202625A1
公开(公告)日：2005-09-15
申请号：US10908872
申请日：2005-05-31
申请人： Fang-Yu Yeh , Chi Lin , Chuang-Hsiang Chen
发明人： Fang-Yu Yeh , Chi Lin , Chuang-Hsiang Chen
IPC分类号： H01L21/336 , H01L29/10 , H01L29/78 , H01L21/8238
CPC分类号： H01L29/66621 , H01L29/1033 , H01L29/7834
摘要： A method of manufacturing a semiconductor device is provided. First, a well region is formed in a substrate and then a mask layer is formed over the substrate. The mask layer and the substrate are patterned to form a first opening in the substrate. Thereafter, a threshold voltage adjustment process is performed. A gate dielectric layer, a first conductive layer and a second conductive layer are sequentially formed inside the first opening. The second conductive layer completely fills the first opening. A portion of the first conductive layer and the second conductive layer are removed so that the upper surface of the first conductive layer and the second conductive layer is slightly below the upper surface of the substrate and hence forms a second opening. A cap layer is formed in second opening and then the mask layer is removed. A source/drain region is formed in the substrate on each side of the first conductive layer. An inter-layer dielectric layer is formed over the substrate. Finally, using the cap layer as a self-aligned mask, a contact opening is formed in the inter-layer dielectric layer.
摘要翻译：提供一种制造半导体器件的方法。首先，在衬底中形成阱区，然后在衬底上形成掩模层。将掩模层和基板图案化以在基板中形成第一开口。此后，执行阈值电压调整处理。在第一开口内依次形成栅介电层，第一导电层和第二导电层。第二导电层完全填充第一开口。去除第一导电层和第二导电层的一部分，使得第一导电层和第二导电层的上表面略低于衬底的上表面，因此形成第二开口。在第二开口中形成盖层，然后去除掩模层。源极/漏极区域形成在第一导电层的每一侧上的衬底中。在衬底上形成层间电介质层。最后，使用盖层作为自对准掩模，在层间电介质层中形成接触开口。

8. 发明申请

US20050106844A1 Method of fabricating a MOSFET device 审中-公开
标题翻译：制造MOSFET器件的方法
公开(公告)号：US20050106844A1
公开(公告)日：2005-05-19
申请号：US10788807
申请日：2004-02-27
申请人： Ming-Sheng Tung , Yueh-Chuan Lee , Fang-Yu Yeh , Chi Lin
发明人： Ming-Sheng Tung , Yueh-Chuan Lee , Fang-Yu Yeh , Chi Lin
IPC分类号： H01L21/336 , H01L29/10
CPC分类号： H01L29/6653 , H01L29/1045 , H01L29/6659 , H01L29/66659
摘要： Ions are implanted into a substrate, using a gate and its sidewall liner on the substrate as the mask, to form a source/drain region in the substrate beneath the liner and adjacent to the two sides of the gate. The liner is etched to reduce its thickness. Then, ions are implanted into the substrate to form a halo doped region surrounding the source/drain region. The halo doped region is closer to the MOSFET channel region and overlaps less with the source/drain region. Therefore, the device threshold voltage can be sustained and the junction leakage can also be minimized.
摘要翻译：将离子以植入基板上的栅极及其侧壁衬垫作为掩模注入到衬底中，以在衬底下面形成源极/漏极区域，并且邻近栅极的两侧。蚀刻衬里以减小其厚度。然后，将离子注入到衬底中以形成围绕源/漏区的卤素掺杂区。卤素掺杂区域更靠近MOSFET沟道区域，并且与源极/漏极区域重叠较小。因此，可以维持器件阈值电压，也可以最小化结漏电。

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