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1. 外观设计

USD858995S1 Tool box 有权
公开(公告)号：USD858995S1
公开(公告)日：2019-09-10
申请号：US29642937
申请日：2018-04-03
申请人： Yi-Fan Chang
设计人： Yi-Fan Chang

2. 发明申请

US20150364933A1 EMERGENCY BATTERY ACTIVATING ASSEMBLY AND EMERGENCY BATTERY ACTIVATING METHOD 审中-公开
标题翻译：紧急电池组件和应急电池的激活方法
公开(公告)号：US20150364933A1
公开(公告)日：2015-12-17
申请号：US14301939
申请日：2014-06-11
申请人： YI-FAN CHANG
发明人： YI-FAN CHANG
IPC分类号： H02J7/00 , B60L11/18
CPC分类号： B60L11/1809 , B60L3/0046 , B60L53/00 , B60L2240/547 , H02J7/0057 , Y02T10/7005 , Y02T10/7072 , Y02T90/14
摘要： The present invention relates to an emergency battery activating assembly applied to car or motorcycle batteries, including at least a preset power supply device, a preset battery, and an activating device. The battery includes at least a conductive portion with a detect voltage value. The activating device is electrically connected to the power supply device and includes an input end, a reference voltage value, and a comparison unit. The input end is electrically connected to the conductive portion. The reference voltage value is set at below 0.5V. The comparison unit is electrically connected to the input end and is used to compare the detect voltage value and the reference voltage value. When the input end is electrically connected to the conductive portion, if the detect voltage value is larger than the reference voltage value, the activating device would activate the power supply device and provide power to the battery. Further, the present invention also relates to an emergence battery activating method.
摘要翻译：本发明涉及应用于汽车或摩托车电池的紧急电池启动组件，其包括至少预设的电源装置，预设电池和启动装置。电池至少包括具有检测电压值的导电部分。激活装置电连接到电源装置，并且包括输入端，参考电压值和比较单元。输入端电连接到导电部分。参考电压值设定在0.5V以下。比较单元电连接到输入端，用于比较检测电压值和参考电压值。当输入端电连接到导电部分时，如果检测电压值大于参考电压值，则启动装置将启动电源装置并向电池供电。此外，本发明还涉及一种电池的起动方法。

3. 发明授权

US08848419B2 Sensing memory element logic states from bit line discharge rate that varies with resistance 有权
标题翻译：从位线放电率传感存储元件逻辑状态随电阻而变化
公开(公告)号：US08848419B2
公开(公告)日：2014-09-30
申请号：US13570305
申请日：2012-08-09
申请人： Jui-Jen Wu , Meng-Fan Chang
发明人： Jui-Jen Wu , Meng-Fan Chang
IPC分类号： G11C11/00
CPC分类号： G11C7/12 , G11C7/065 , G11C7/14 , G11C11/419
摘要： A digital memory element has a sense circuit latch to read the value stored in a bit cell. Before addressing a word line, the bit lines are precharged. During the read operation, a bit line is coupled to a supply voltage through a bit cell memory element that has different resistances at logic states “0” and “1.” A reference bit line is coupled to the supply voltage through a comparison resistance value, especially a resistance between high and low resistance of the memory element in the two logic states. Voltages on the bit line and reference bit line ramp toward a switching threshold at rates related to the resistance values. The first line to discharge to switching threshold voltage sets the sense circuit latch.
摘要翻译：数字存储元件具有用于读取存储在位单元中的值的读出电路锁存器。在寻址字线之前，位线是预先充电的。在读取操作期间，位线通过位逻辑状态“0”和“1”处具有不同电阻的位单元存储元件耦合到电源电压。参考位线通过比较电阻值耦合到电源电压特别是在两个逻辑状态下存储元件的高电阻和低电阻之间的电阻。在与电阻值相关的速率下，位线上的电压和参考位线斜坡转向切换阈值。第一行放电到开关阈值电压设置感测电路锁存器。

4. 发明授权

US08829887B2 Pulse type layer-ID detector for 3D-IC and method of the same 有权
标题翻译：用于3D-IC的脉冲型层ID检测器及其方法
公开(公告)号：US08829887B2
公开(公告)日：2014-09-09
申请号：US12896429
申请日：2010-10-01
申请人： Ming-Pin Chen , Meng-Fan Chang , Wei-Cheng Wu
发明人： Ming-Pin Chen , Meng-Fan Chang , Wei-Cheng Wu
IPC分类号： G01R31/28
CPC分类号： H03K21/023 , H03K21/026 , H03K21/38
摘要： A 3D-IC detector for each layer of a stacked device comprises a pulse generator to receive an initial signal and generate a pulse-in signal to a next stage detector. A latch is coupled to the pulse generator to receive an output signal from the pulse generator and generate a layer identifying signal. A counter is coupled to previous stage detector and the initial signal to perform a counting operation; and an adder coupled to the counter to add a number to a counting output from the counter and input added signal to the pulse generator.
摘要翻译：用于层叠器件的每层的3D-IC检测器包括用于接收初始信号并向下一级检测器产生脉冲信号的脉冲发生器。锁存器耦合到脉冲发生器以接收来自脉冲发生器的输出信号并产生层识别信号。计数器耦合到前一级检测器和初始信号以执行计数操作; 以及加法器，其耦合到计数器以向计数器的计数输出添加数字，并将附加的信号输入到脉冲发生器。

5. 发明授权

US08547755B2 Method and apparatus of performing an erase operation on a memory integrated circuit 有权
标题翻译：在存储器集成电路上执行擦除操作的方法和装置
公开(公告)号：US08547755B2
公开(公告)日：2013-10-01
申请号：US13708102
申请日：2012-12-07
申请人： Yi-Fan Chang , Cheng Ming Yih , Su-chueh Lo , Jian Shing Liu , Kuen Long Chang , Chun-Hsiung Hung
发明人： Yi-Fan Chang , Cheng Ming Yih , Su-chueh Lo , Jian Shing Liu , Kuen Long Chang , Chun-Hsiung Hung
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C16/14 , G11C16/344 , G11C16/3477
摘要： Various discussed approaches include an improved grouping of edge word lines and center word lines of an erase group during erase verify and erase sub-operations of an erase operation. In another approach, changed voltage levels of edge word lines to address the over-erase issue of the erase group, and also improve erase time performance. Another approach uses dummy word lines.
摘要翻译：各种讨论的方法包括在擦除验证和擦除擦除操作的子操作期间改进擦除组的边缘字线和中心字线的分组。在另一种方法中，改变边缘字线的电压电平以解决擦除组的过擦除问题，并且还提高擦除时间性能。另一种方法使用虚拟字线。

6. 发明申请

US20130148402A1 CONTROL SCHEME FOR 3D MEMORY IC 有权
标题翻译： 3D存储IC控制方案
公开(公告)号：US20130148402A1
公开(公告)日：2013-06-13
申请号：US13524980
申请日：2012-06-15
申请人： Meng-Fan CHANG , Wei-Cheng Wu , Tsung-Hsien Huang , Chien-Yuan Chen
发明人： Meng-Fan CHANG , Wei-Cheng Wu , Tsung-Hsien Huang , Chien-Yuan Chen
IPC分类号： G11C5/06
CPC分类号： G11C29/023 , G11C8/08 , G11C11/417 , G11C29/028 , G11C29/04 , G11C29/26 , G11C2029/1202 , G11C2029/1206 , G11C2029/2602
摘要： The present invention discloses a control scheme for 3D memory IC that includes a master chip and at least one slave chip. The master chip includes a main memory core, a first local timer, an I/O buffer, a first pad and a second pad. The at least one slave chip is stacked with the master chip. Each of the slave chip includes a slave memory core, a second local timer and a third pad. A first TSV is coupled to the first pad and the third pad. A logic control circuit layer includes a logic control circuit and a fourth pad, and the logic control circuit is coupled to the fourth pad. A second TSV is coupled to the second pad and the fourth pad.
摘要翻译：本发明公开了一种包括主芯片和至少一个从芯片的3D存储器IC的控制方案。主芯片包括主存储器核心，第一本地定时器，I / O缓冲器，第一焊盘和第二焊盘。至少一个从芯片与主芯片堆叠。每个从芯片包括从存储器核心，第二本地定时器和第三焊盘。第一TSV耦合到第一焊盘和第三焊盘。逻辑控制电路层包括逻辑控制电路和第四焊盘，逻辑控制电路耦合到第四焊盘。第二TSV耦合到第二焊盘和第四焊盘。

7. 发明授权

US08390365B2 Charge pump system for low-supply voltage 有权
标题翻译：电源泵系统为低电源电压
公开(公告)号：US08390365B2
公开(公告)日：2013-03-05
申请号：US12906302
申请日：2010-10-18
申请人： Meng-Fan Chang , Shin-Jang Shen , Yi-Lun Lu
发明人： Meng-Fan Chang , Shin-Jang Shen , Yi-Lun Lu
IPC分类号： H02M3/00 , G05F3/08
CPC分类号： G11C7/222
摘要： A charge pump system for low-supply voltage includes: a clock generator to generate a plurality of clock signals; a clock pump circuit coupled to said clock generator to generate high voltage; a level shifter coupled to said clock generator and said clock pump circuit to generate a plurality of HV (high voltage) clock signals; a main pump circuit coupled to said clock generator and said level shifter to generate output voltage.
摘要翻译：用于低电源电压的电荷泵系统包括：时钟发生器，用于产生多个时钟信号; 时钟泵电路，耦合到所述时钟发生器以产生高电压; 电平移位器，耦合到所述时钟发生器和所述时钟泵电路，以产生多个HV（高电压）时钟信号; 主泵电路耦合到所述时钟发生器和所述电平移位器以产生输出电压。

8. 发明授权

US08339861B2 Method and apparatus of performing an erase operation on a memory integrated circuit 有权
标题翻译：在存储器集成电路上执行擦除操作的方法和装置
公开(公告)号：US08339861B2
公开(公告)日：2012-12-25
申请号：US12834686
申请日：2010-07-12
申请人： Yi-Fan Chang , Cheng Ming Yih , Su-chueh Lo , Jian Shing Liu , Kuen-Long Chang , Chun-Hsiung Hung
发明人： Yi-Fan Chang , Cheng Ming Yih , Su-chueh Lo , Jian Shing Liu , Kuen-Long Chang , Chun-Hsiung Hung
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C16/14 , G11C16/344 , G11C16/3477
摘要： Various discussed approaches include an improved grouping of edge word lines and center word lines of an erase group during erase verify and erase sub-operations of an erase operation. In another approach, changed voltage levels of edge word lines to address the over-erase issue of the erase group, and also improve erase time performance. Another approach uses dummy word lines.
摘要翻译：各种讨论的方法包括在擦除验证和擦除擦除操作的子操作期间改进擦除组的边缘字线和中心字线的分组。在另一种方法中，改变边缘字线的电压电平以解决擦除组的过擦除问题，并且还提高擦除时间性能。另一种方法使用虚拟字线。

9. 发明申请

US20120300553A1 Method and Apparatus of Performing An Erase Operation On A Memory Integrated Circuit 有权
标题翻译：在存储器集成电路中执行擦除操作的方法和装置
公开(公告)号：US20120300553A1
公开(公告)日：2012-11-29
申请号：US13567817
申请日：2012-08-06
申请人： Yi-Fan Chang , Su-chueh Lo , Cheng Ming Yih , Ta Kang Chu , Chu Ching Wu , Kuo Yu Liao , Ken Hui Chen , Kuen-Long Chang , Chun-Hsiung Hung
发明人： Yi-Fan Chang , Su-chueh Lo , Cheng Ming Yih , Ta Kang Chu , Chu Ching Wu , Kuo Yu Liao , Ken Hui Chen , Kuen-Long Chang , Chun-Hsiung Hung
IPC分类号： G11C16/04
CPC分类号： G11C11/5635 , G11C16/0483 , G11C16/3418
摘要： Various discussed approaches improve the over erase issue and the coupling effect, and include (A) multilevel contacts between (i) the first outer selected word line of an erase group, and (ii) the first unselected word line outside the ease group neighboring the first outer selected word line; (B) a sufficient separation distance between (i) the first outer selected word line of an erase group, and (ii) the first unselected word line outside the ease group neighboring the first outer selected word line. These are examples of electrically isolating (i) the first outer selected word line of an erase group, from (ii) the first unselected word line outside the ease group neighboring the first outer selected word line.
摘要翻译：各种讨论的方法改进了过度擦除问题和耦合效应，并且包括（A）（i）擦除组的第一外部选定字线之间的多电平接触，以及（ii）与易失性组相邻的第一未选择字线第一外选字线; （B）在（i）擦除组的第一外部选择字线之间的足够的间隔距离，和（ii）与第一外部选择字线相邻的容易组之外的第一未选择字线。这些是将（i）擦除组的第一外部选择的字线从（ii）与第一外部选择字线相邻的易用组之外的第一未选择字线电隔离的示例。

10. 发明申请

US20120092063A1 Charge pump system for low-supply voltage 有权
标题翻译：电源泵系统为低电源电压
公开(公告)号：US20120092063A1
公开(公告)日：2012-04-19
申请号：US12906302
申请日：2010-10-18
申请人： Meng-Fan Chang , Shin-Jang Shen , Yi-Lun Lu
发明人： Meng-Fan Chang , Shin-Jang Shen , Yi-Lun Lu
IPC分类号： G05F3/02
CPC分类号： G11C7/222
摘要： The present invention discloses a charge pump system for low-supply voltage including: a clock generator to generate a plurality of clock signals; a clock pump circuit coupled to said clock generator to generate high voltage; a level shifter coupled to said clock generator and said clock pump circuit to generate a plurality of HV (high voltage)-clock signals; a main pump circuit coupled to said clock generator and said level shifter to generate output voltage.
摘要翻译：本发明公开了一种用于低电源电压的电荷泵系统，包括：时钟发生器，用于产生多个时钟信号; 时钟泵电路，耦合到所述时钟发生器以产生高电压; 电平移位器，耦合到所述时钟发生器和所述时钟泵电路，以产生多个HV（高电压）时钟信号; 主泵电路耦合到所述时钟发生器和所述电平移位器以产生输出电压。

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