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1. 发明授权

US08778772B2 Method of forming transistor with increased gate width 有权
标题翻译：具有增加栅极宽度的晶体管形成方法
公开(公告)号：US08778772B2
公开(公告)日：2014-07-15
申请号：US13348101
申请日：2012-01-11
申请人： Chung Foong Tan , Maciej Wiatr , Peter Javorka , Falong Zhou
发明人： Chung Foong Tan , Maciej Wiatr , Peter Javorka , Falong Zhou
IPC分类号： H01L21/283
CPC分类号： H01L29/66545 , H01L21/28123 , H01L21/76232 , H01L29/42376
摘要： Methods of forming transistor devices having an increased gate width dimension are disclosed. In one example, the method includes forming an isolation structure in a semiconducting substrate, wherein the isolation structure defines an active region in the substrate, performing an ion implantation process on the isolation structure to create a damaged region in the isolation structure and, after performing the implantation process, performing an etching process to remove at least a portion of the damaged region to define a recess in the isolation structure, wherein a portion of the recess extends below an upper surface of the substrate and exposes a sidewall of the active region. The method further includes forming a gate insulation layer above the active region, wherein a portion of the insulation layer extends into the recess, and forming a gate electrode above the insulation layer, wherein a portion of the gate electrode extends into the recess.
摘要翻译：公开了具有增加的栅极宽度尺寸的晶体管器件的形成方法。在一个示例中，该方法包括在半导体衬底中形成隔离结构，其中隔离结构限定衬底中的有源区，在隔离结构上执行离子注入工艺以在隔离结构中产生受损区域，并且在执行所述注入工艺，执行蚀刻工艺以去除所述损坏区域的至少一部分以在所述隔离结构中限定凹部，其中所述凹部的一部分在所述衬底的上表面下方延伸并暴露所述有源区的侧壁。该方法还包括在有源区上方形成栅极绝缘层，其中绝缘层的一部分延伸到凹槽中，并在绝缘层之上形成栅电极，其中栅电极的一部分延伸到凹槽中。

2. 发明申请

US20130178045A1 Method of Forming Transistor with Increased Gate Width 有权
标题翻译：形成具有增加的栅极宽度的晶体管的方法
公开(公告)号：US20130178045A1
公开(公告)日：2013-07-11
申请号：US13348101
申请日：2012-01-11
申请人： Chung Foong Tan , Maciej Wiatr , Peter Javorka , Falong Zhou
发明人： Chung Foong Tan , Maciej Wiatr , Peter Javorka , Falong Zhou
IPC分类号： H01L21/283
CPC分类号： H01L29/66545 , H01L21/28123 , H01L21/76232 , H01L29/42376
摘要： Methods of forming transistor devices having an increased gate width dimension are disclosed. In one example, the method includes forming an isolation structure in a semiconducting substrate, wherein the isolation structure defines an active region in the substrate, performing an ion implantation process on the isolation structure to create a damaged region in the isolation structure and, after performing the implantation process, performing an etching process to remove at least a portion of the damaged region to define a recess in the isolation structure, wherein a portion of the recess extends below an upper surface of the substrate and exposes a sidewall of the active region. The method further includes forming a gate insulation layer above the active region, wherein a portion of the insulation layer extends into the recess, and forming a gate electrode above the insulation layer, wherein a portion of the gate electrode extends into the recess.
摘要翻译：公开了具有增加的栅极宽度尺寸的晶体管器件的形成方法。在一个示例中，该方法包括在半导体衬底中形成隔离结构，其中隔离结构限定衬底中的有源区，在隔离结构上执行离子注入工艺以在隔离结构中产生受损区域，并且在执行所述注入工艺，执行蚀刻工艺以去除所述损坏区域的至少一部分以在所述隔离结构中限定凹部，其中所述凹部的一部分在所述衬底的上表面下方延伸并暴露所述有源区的侧壁。该方法还包括在有源区上方形成栅极绝缘层，其中绝缘层的一部分延伸到凹槽中，并在绝缘层之上形成栅电极，其中栅电极的一部分延伸到凹槽中。

3. 发明申请

US20130175585A1 Methods of Forming Faceted Stress-Inducing Stressors Proximate the Gate Structure of a Transistor 审中-公开
标题翻译：形成面应力诱导应力的方法近似于晶体管的栅极结构
公开(公告)号：US20130175585A1
公开(公告)日：2013-07-11
申请号：US13348184
申请日：2012-01-11
申请人： Chung Foong Tan , Maciej Wiatr , Stephan Kronholz , Falong Zhou , Ying Hao Hsieh
发明人： Chung Foong Tan , Maciej Wiatr , Stephan Kronholz , Falong Zhou , Ying Hao Hsieh
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/1054 , H01L29/165 , H01L29/66628 , H01L29/66636 , H01L29/66651 , H01L29/7834 , H01L29/7848
摘要： Disclosed herein are various methods of forming faceted stress-inducing stressors proximate the gate structure of a transistor. In one example, a method includes forming a first recess in an active region of a semiconducting substrate, forming a first semiconductor material in the first recess and forming a gate structure above the first semiconductor material. In this example, the method includes the additional steps of performing a crystalline orientation-dependent etching process on the first semiconductor material to define a plurality of second recesses proximate the gate structure, wherein each of the second recesses has a faceted edge, and forming a first region of stress-inducing semiconductor material in each of the second recesses, wherein each of the first regions of stress-inducing semiconductor material has a faceted edge that engages a corresponding faceted edge in one of the second recesses.
摘要翻译：本文公开了在晶体管的栅极结构附近形成面应力诱导应力源的各种方法。在一个示例中，一种方法包括在半导体衬底的有源区中形成第一凹槽，在第一凹槽中形成第一半导体材料，并在第一半导体材料之上形成栅极结构。在该示例中，该方法包括对第一半导体材料执行结晶取向依赖蚀刻工艺以限定靠近栅极结构的多个第二凹槽的附加步骤，其中每个第二凹槽具有刻面边缘，并且形成在每个第二凹部中的应力诱导半导体材料的第一区域，其中所述第一应力诱导半导体材料区域中的每一个具有与所述第二凹部中的一个凹部中的相应的刻面边缘接合的刻面边缘。

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