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1. 发明授权

US06188241B1 Microcontroller having a block of logic configurable to perform a selected logic function and to produce output signals coupled to corresponding I/O pads according to a predefined hardware interface 有权
标题翻译：微控制器具有逻辑块，其可配置为执行选定的逻辑功能并根据预定义的硬件接口产生耦合到对应的I / O焊盘的输出信号
公开(公告)号：US06188241B1
公开(公告)日：2001-02-13
申请号：US09311448
申请日：1999-05-14
申请人： Lloyd W. Gauthier , Carl K. Wakeland , Faheem Hayat , David F. Tobias
发明人： Lloyd W. Gauthier , Carl K. Wakeland , Faheem Hayat , David F. Tobias
IPC分类号： H03K19177
CPC分类号： G06F15/7867
摘要： A microcontroller is presented having a block of logic configurable to perform a selected logic function and to produce output signals coupled to corresponding I/O pads according to a predefined hardware interface. The microcontroller includes a central processing unit (CPU), a first set of I/O pads, and a configurable logic block (CLB) all formed upon a single monolithic semiconductor substrate. The CPU is configured to execute instructions, preferably x86 instructions. The CPU produces CPU output signals during instruction execution. The CLB is coupled between the CPU output signals and the first set of I/O pads, and is configurable to perform a logic function selected from a predefined set of logic functions. Each member of the set of logic functions has an associated hardware interface including a signal table which defines a correspondence between CLB input/output signals and members of the first set of I/O pads. The microcontroller also preferably includes a test/program core coupled to a second set of I/O pads and to the CLB. The test/program core produces programming signals in response to signals received via the second set of I/O pads. The programming signals cause the CLB to perform the selected logic function. When programmed, the CLB produces CLB output signals in response to the CPU output signals. Each of the CLB output signals is coupled to one or more of the members of the first set of I/O pads according to the hardware interface of the selected logic function.
摘要翻译：呈现具有可配置为执行选定逻辑功能并根据预定义的硬件接口产生耦合到相应I / O焊盘的输出信号的逻辑块的微控制器。微控制器包括中央处理单元（CPU），第一组I / O焊盘以及全部形成在单个单片半导体衬底上的可配置逻辑块（CLB）。 CPU配置为执行指令，最好是x86指令。 CPU在指令执行过程中产生CPU输出信号。 CLB耦合在CPU输出信号和第一组I / O焊盘之间，并且可配置为执行从预定义的一组逻辑功能中选择的逻辑功能。逻辑功能集合中的每个成员具有相关联的硬件接口，其包括定义CLB输入/输出信号与第一组I / O焊盘组件之间的对应关系的信号表。微控制器还优选地包括耦合到第二组I / O焊盘和CLB的测试/程序核心。测试/程序核心响应于经由第二组I / O焊盘接收到的信号产生编程信号。编程信号使CLB执行选定的逻辑功能。当编程时，CLB响应于CPU输出信号产生CLB输出信号。根据所选择的逻辑功能的硬件接口，每个CLB输出信号被耦合到第一组I / O焊盘的一个或多个成员。

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