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1. 发明授权

US6138204A Multi bus access memory 失效
标题翻译：多总线访问存储器
公开(公告)号：US6138204A
公开(公告)日：2000-10-24
申请号：US992466
申请日：1997-12-17
申请人： Yossi Amon , Moshe Tarrab , Eytan Engel
发明人： Yossi Amon , Moshe Tarrab , Eytan Engel
IPC分类号： G11C7/10 , G06F13/16
CPC分类号： G11C7/1048 , G11C7/1051 , G11C7/1078
摘要： The present invention relates to memory and methods for storing/retrieving data in/from the memory that is accessed by at least two distinct data uses of different actual word widths. A memory for storing addressable binary data comprises a data storage organized in rows and columns of bit array cells, row address decoder and driver for addressing a selected row of bit array cells, column drivers for driving selected columns of bit array cells, and a bus switch port for selectively transferring data between the data storage and a first data bus with a first bus word width p and a second data bus with a second bus word width q smaller than the first bus word width p.
摘要翻译：本发明涉及用于存储/检索来自存储器的数据的存储器和方法，所述存储器和数据由不同实际字宽的至少两个不同数据使用访问。用于存储可寻址二进制数据的存储器包括组织成位阵列单元的行和列的数据存储器，行地址解码器和用于寻址所选行的位阵列单元的驱动器，用于驱动位阵列单元的选定列的列驱动器和总线开关端口，用于在具有第一总线字宽度p的数据存储器和第一数据总线之间选择性地传送数据，并且具有小于第一总线字宽度p的第二总线字宽度q的第二数据总线。

2. 发明授权

US06529567B1 Electronic apparatus and method for receiving noisy signals 有权
标题翻译：用于接收噪声信号的电子设备和方法
公开(公告)号：US06529567B1
公开(公告)日：2003-03-04
申请号：US09265221
申请日：1999-03-10
申请人： Eran Pisek , Moshe Tarrab , Eytan Engel
发明人： Eran Pisek , Moshe Tarrab , Eytan Engel
IPC分类号： H04L2706
CPC分类号： H04L25/067
摘要： An electronic apparatus receives a noisy signal and produces and stores hard data and soft data. It has a first portion (210, 310) for receiving electromagnetic signals and producing hard data and soft data, and a second portion (200, 300) for storing soft data and hard data concerning a particular signal at a single location in a memory bank (270, 370), preferably at the same memory address. Hard data and soft data can be stored in consecutive memory cells. Hard data can overlap soft data. If hard data overlaps soft data, it preferably overlaps soft data least significant bits. The second portion (200, 300) has a memory bank (270, 370), a controller (260, 360) and also can have a synchronizer (390) for synchronizing between soft data and hard data concerning the same input signal.
摘要翻译：电子设备接收噪声信号并产生并存储硬数据和软数据。它具有用于接收电磁信号并产生硬数据和软数据的第一部分（210,310），以及用于在存储器组中的单个位置存储关于特定信号的软数据和硬数据的第二部分（200,300）（270,370），优选地在相同的存储器地址处。硬数据和软数据可以存储在连续的存储单元中。硬数据可以重叠软数据。如果硬数据与软数据重叠，则它优选与软数据最低有效位重叠。第二部分（200,300）具有存储体（270,370），控制器（260,360），并且还可以具有用于在软数据和有关相同输入信号的硬数据之间同步的同步器（390）。

3. 发明授权

US6097889A Signal processing apparatus with stages in a signal path operating as LFSR of alternable type and method for processing signals 失效
标题翻译：信号处理装置，其信号路径中的阶段以可交替类型的LFSR和用于处理信号的方法操作
公开(公告)号：US6097889A
公开(公告)日：2000-08-01
申请号：US880956
申请日：1997-06-23
申请人： Moshe Tarrab , Eytan Engel , Eli Borowitz , Leonid Belotserkovsky
发明人： Moshe Tarrab , Eytan Engel , Eli Borowitz , Leonid Belotserkovsky
IPC分类号： G06F7/58 , H03K3/84 , G06F15/00
CPC分类号： G06F7/584 , H03K3/84 , G06F2207/583
摘要： According to the present invention, an LFSR (300) has a propagation path (30) of serially coupled stages (65) and gates (80-3, 80-4), a feedforward path (10) of gates (80-1) and a feedback path (20) of gates (80-2). Depending on control signals (P, B, M), the gates (80-1, 80-2, 80-3, 80-4) are either active gates and operate as xor-gates or passive gates and operate as transfer gates. Feedforward and feedback signals are derived from input and output signals and can be supplied to any stage (65), so that characteristic polynomials of the input-output function are variable. The LFSR can fully or partly operate as a TYPE 1 or TYPE 2 LFSR which enables the execution of different algorithms on one hardware base.
摘要翻译：根据本发明，LFSR（300）具有串联耦合级（65）和门（80-3,80-4）的传播路径（30），门（80-1）的前馈路径（10）和门（80-2）的反馈路径（20）。根据控制信号（P，B，M），栅极（80-1,80-2,80-3,80-4）是有源栅极，并作为半门或无源栅极工作，并作为传输门。前馈和反馈信号来自输入和输出信号，并且可以提供给任何级（65），使得输入 - 输出功能的特征多项式是可变的。 LFSR可以完全或部分地作为TYPE 1或TYPE 2 LFSR运行，这使得在一个硬件基础上执行不同的算法。

4. 发明授权

US5729153A Output buffer with oscillation damping 失效
标题翻译：具有振荡阻尼的输出缓冲器
公开(公告)号：US5729153A
公开(公告)日：1998-03-17
申请号：US559864
申请日：1995-11-20
申请人： Yachin Afek , Vladimir Koifman , Natan Baron , Eytan Engel
发明人： Yachin Afek , Vladimir Koifman , Natan Baron , Eytan Engel
IPC分类号： H03K19/003 , H03K19/0948
CPC分类号： H03K19/00361
摘要： Oscillation of the output (16, 17) of an integrated circuit output buffer (43) is automatically damped by sensing ground lead (18) transients as the buffer output (16, 17) changes, and when the ground lead (18) swing is large enough, using the sensed change to apply a turn-off signal of the appropriate polarity to a transistor (N1) serially placed in the output buffer (43) to add resistance during the transition. The added resistance damps out the oscillations quickly to prevent rebound of the buffer output voltage past the logic transition threshold (Vol). An RC time constant (R1, C1) controls the duration of the added resistance which disappears after the transition is complete. The action of a damping control circuit (45) is speed dependent so that greater damping is provided for fast transitions when oscillations would be more sever and no damping during slow transitions when damping is not needed.
摘要翻译：集成电路输出缓冲器（43）的输出（16,17）的振荡由于缓冲器输出（16,17）变化而通过感测接地引线（18）瞬变而被自动衰减，并且当接地引线（18）摆动为足够大，使用感测到的改变将适当极性的关断信号施加到串联放置在输出缓冲器（43）中的晶体管（N1），以在转换期间增加电阻。增加的电阻快速阻止振荡，以防止缓冲器输出电压的反弹超过逻辑转换阈值（Vol）。 RC时间常数（R1，C1）控制转换完成后消失的增加电阻的持续时间。阻尼控制电路（45）的作用是速度依赖性的，因此当不需要阻尼时，振荡将更加严密，并且在缓慢转变期间没有阻尼，因此为快速过渡提供更大的阻尼。

5. 发明授权

US5966029A Multi-bit exclusive or 失效
标题翻译：多位独占或
公开(公告)号：US5966029A
公开(公告)日：1999-10-12
申请号：US893043
申请日：1997-07-15
申请人： Moshe Tarrab , Eytan Engel , Natan Baron , Dan Kuzmin
发明人： Moshe Tarrab , Eytan Engel , Natan Baron , Dan Kuzmin
IPC分类号： H03K19/21
CPC分类号： H03K19/21
摘要： The present invention relates to multi-bit exclusive-or (XOR) gates (60), including those where N parallel input bits (36, 38) are XORed with one data input bit (52). A modular approach is made using only one basic cell (30) for various implementations with different propagation delays. An N-bit XOR comprises basic cells (30) of adjacent first and second XOR gates (32, 34). Each first XOR gate (32) processes as input two of said N primary input bits (36, 38) and each second XOR gate (34) processes as input bits output bits of first or second XOR gates (32, 34) or the input data bit (52). This structure makes it possible to create an array of identical basic cells which is very suitable for VLSI implementation. There are few lines of connections between the different cells in the cell array which leads to substantial reduction in propagation delay without adding substantial wiring or layout complexity.
摘要翻译：本发明涉及多位异或（XOR）门（60），包括其中N个并行输入位（36,38）与一个数据输入位（52）进行异或运算的门。仅使用一个基本单元（30）进行模块化处理，用于具有不同传播延迟的各种实现。 N位XOR包括相邻的第一和第二异或门（32,34）的基本单元（30）。每个第一XOR门（32）作为所述N个主要输入位（36,38）中的两个进行处理，并且每个第二异或门（34）作为第一或第二异或门（32,34）的输入位或输入数据位（52）。该结构使得可以创建非常适合VLSI实现的相同基本单元阵列。在单元阵列中的不同单元之间存在很少的连接线，导致传播延迟的显着降低，而不增加实质的布线或布局的复杂性。

6. 发明授权

US5751178A Apparatus and method for shifting signal levels 失效
标题翻译：用于移位信号电平的装置和方法
公开(公告)号：US5751178A
公开(公告)日：1998-05-12
申请号：US767094
申请日：1996-12-05
申请人： Joseph Shor , Eytan Engel , Natan Baron
发明人： Joseph Shor , Eytan Engel , Natan Baron
IPC分类号： H03K17/10 , H03K19/0185 , H03K5/153
CPC分类号： H03K17/102 , H03K19/018521
摘要： The electronic circuit (100) of the invention receives first signals DATA (170) having logical "1" at high (VCCH) or low (VCCL) levels and logical "0" at reference level (ZERO) and generates second signals OUT (186) between high level (VCCH) and reference level (ZERO) without changing the information. The circuit comprises a first switch (161) and a second switch (161) serially coupled together to a common output node (103). The first switch (162) is controlled by a control signal (CTRL) derived from DATA, OUT, or optionally from a clock signal CLK. The first switch (161) is switched off before the second switch (162) is switched off. Contention (conducting at the same time) is thereby avoided and the first switch (161) and the second switch (162) can be implemented by substantially equal-sized components.
摘要翻译：本发明的电子电路（100）在高（VCCH）或低（VCCL）电平处接收具有逻辑“1”的第一信号DATA（170），并在基准电平（ZERO）处接收逻辑“0”，并产生第二信号OUT（186 ）在高电平（VCCH）和参考电平（ZERO）之间，而不改变信息。电路包括串联耦合到公共输出节点（103）的第一开关（161）和第二开关（161）。第一开关（162）由从DATA，OUT或可选地从时钟信号CLK导出的控制信号（CTRL）来控制。在第二开关（162）关闭之前，第一开关（161）被断开。因此避免了同时进行的竞争（第一开关161和第二开关162）可以通过基本相等的部件来实现。

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