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1. 发明申请

US20110189846A1 METHODS OF MANUFACTURING NON-VOLATILE MEMORY DEVICES 审中-公开
标题翻译：制造非易失性存储器件的方法
公开(公告)号：US20110189846A1
公开(公告)日：2011-08-04
申请号：US13020979
申请日：2011-02-04
申请人： Jeong Gil Lee , Chang-Won Lee , Sang-Woo Lee , Sun-Woo Lee , Ki-Hyun Hwang , Jae-Hwa Park , Eun-Ji Jung
发明人： Jeong Gil Lee , Chang-Won Lee , Sang-Woo Lee , Sun-Woo Lee , Ki-Hyun Hwang , Jae-Hwa Park , Eun-Ji Jung
IPC分类号： H01L21/28
CPC分类号： H01L21/28
摘要： A method of manufacturing a non-volatile memory device including a tunnel oxide layer, a preliminary charge storing layer and a dielectric layer on a semiconductor layer is disclosed. A first polysilicon layer is formed on the dielectric layer. A barrier layer and a second polysilicon layer are formed on the first polysilicon layer. The second polysilicon layer, the barrier layer, the first polysilicon layer, the dielectric layer, the preliminary charge storing layer and the tunnel oxide layer are patterned to form a tunnel layer pattern, a charge storing layer pattern, a dielectric layer pattern, a first control gate pattern, a barrier layer pattern and a second polysilicon pattern. A nickel layer is formed on the second polysilicon layer. Heat treatment is performed with respect to the second polysilicon pattern and the nickel layer to form a second control gate pattern including NiSi on the barrier layer pattern.
摘要翻译：公开了一种在半导体层上制造包括隧道氧化物层，初电电荷存储层和电介质层的非易失性存储器件的方法。在介电层上形成第一多晶硅层。在第一多晶硅层上形成阻挡层和第二多晶硅层。对第二多晶硅层，势垒层，第一多晶硅层，电介质层，初电电荷存储层和隧道氧化物层进行图案化以形成隧道层图案，电荷存储层图案，介电层图案，第一控制栅极图案，势垒层图案和第二多晶硅图案。在第二多晶硅层上形成镍层。对第二多晶硅图案和镍层进行热处理，以在阻挡层图案上形成包括NiSi的第二控制栅极图案。

2. 发明申请

US20100237423A1 SEMICONDUCTOR DEVICES INCLUDING BURIED BIT LINES 有权
标题翻译：半导体器件，包括BINIIT位线
公开(公告)号：US20100237423A1
公开(公告)日：2010-09-23
申请号：US12791692
申请日：2010-06-01
申请人： Jong-Ho Yun , Byung-Hee Kim , Dae-Yong Kim , Hyun-Su Kim , Eun-Ji Jung , Eun-Ok Lee
发明人： Jong-Ho Yun , Byung-Hee Kim , Dae-Yong Kim , Hyun-Su Kim , Eun-Ji Jung , Eun-Ok Lee
IPC分类号： H01L27/088
CPC分类号： H01L27/10885 , H01L27/10876
摘要： A semiconductor device includes a plurality of channel structures on a semiconductor substrate. A bit line groove having opposing sidewalls is defined between sidewalls of adjacent ones of the plurality of channel structures. A plurality of bit lines are formed on corresponding ones of the opposing sidewalls, and the plurality of bit lines are electrically isolated from each other
摘要翻译：半导体器件包括半导体衬底上的多个沟道结构。具有相对侧壁的位线槽限定在多个通道结构中的相邻侧壁之间。多个位线形成在对置的相对的侧壁的相应的一个上，多个位线彼此电隔离

3. 发明授权

US07687331B2 Stacked semiconductor device and method of fabrication 有权
标题翻译：叠层半导体器件及其制造方法
公开(公告)号：US07687331B2
公开(公告)日：2010-03-30
申请号：US12108591
申请日：2008-04-24
申请人： Hyun-Su Kim , Gil-Heyun Choi , Jong-Ho Yun , Sug-Woo Jung , Eun-Ji Jung
发明人： Hyun-Su Kim , Gil-Heyun Choi , Jong-Ho Yun , Sug-Woo Jung , Eun-Ji Jung
IPC分类号： H01L21/84
CPC分类号： H01L27/0688 , H01L21/8221
摘要： A stacked semiconductor device comprises a lower transistor formed on a semiconductor substrate, a lower interlevel insulation film formed on the semiconductor substrate over the lower transistor, an upper transistor formed on the lower interlayer insulation film over the lower transistor, and an upper interlevel insulation film formed on the lower interlevel insulation film over the upper transistor. The stacked semiconductor device further comprises a contact plug connected between a drain or source region of the lower transistor and a source or drain region of the upper transistor, and an extension layer connected to a lateral face of the source or drain region of the upper transistor to enlarge an area of contact between the source or drain region of the upper transistor and a side of the contact plug.
摘要翻译：叠层半导体器件包括形成在半导体衬底上的下晶体管，形成在半导体衬底上的下层晶体管上的下层间绝缘膜，形成在下晶体管上的下层间绝缘膜上的上晶体管，以及上层间绝缘膜形成在上层晶体管上的较低层间绝缘膜上。叠层半导体器件还包括连接在下晶体管的漏极或源极区域与上部晶体管的源极或漏极区域之间的接触插塞以及连接到上部晶体管的源极或漏极区域的侧面的延伸层以扩大上部晶体管的源极或漏极区域与接触插塞的一侧之间的接触面积。

4. 发明申请

US20080211039A1 Nonvolatile memory devices having metal silicide nanocrystals, methods of forming metal silicide nanocrystals, and methods of forming nonvolatile memory devices having metal silicide nanocrystals 审中-公开
标题翻译：具有金属硅化物纳米晶体的非易失性存储器件，形成金属硅化物纳米晶体的方法以及形成具有金属硅化物纳米晶体的非易失性存储器件的方法
公开(公告)号：US20080211039A1
公开(公告)日：2008-09-04
申请号：US11999704
申请日：2007-12-06
申请人： Xiaofeng Wang , Eun-Ji Jung , In-Seok Yeo
发明人： Xiaofeng Wang , Eun-Ji Jung , In-Seok Yeo
IPC分类号： H01L29/78 , H01L21/44
CPC分类号： H01L29/7881 , B82Y10/00 , H01L29/40114 , H01L29/42332 , H01L29/66825 , H01L29/7833
摘要： A nonvolatile memory device includes a semiconductor substrate. A charge storage insulating film containing metal silicide nanocrystals is on the substrate. A gate electrode is on the charge storage insulating film. Related methods of forming metal silicide nanocrystals, and methods of forming nonvolatile memory devices including metal silicide nanocrystals, are also disclosed.
摘要翻译：非易失性存储器件包括半导体衬底。含有金属硅化物纳米晶体的电荷存储绝缘膜位于基板上。栅电极位于电荷存储绝缘膜上。还公开了形成金属硅化物纳米晶体的相关方法，以及形成包括金属硅化物纳米晶体的非易失性存储器件的方法。

5. 发明申请

US20080020567A1 Method of Manufacturing a Semiconductor Device 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：US20080020567A1
公开(公告)日：2008-01-24
申请号：US11777536
申请日：2007-07-13
申请人： Eun-Ji Jung , Jong-Ho Yun , Dae-Yong Kim , Hyun-Su Kim , Byung-Hee Kim , Eun-Ok Lee
发明人： Eun-Ji Jung , Jong-Ho Yun , Dae-Yong Kim , Hyun-Su Kim , Byung-Hee Kim , Eun-Ok Lee
IPC分类号： H01L21/441
CPC分类号： H01L21/28097 , H01L29/4975 , H01L29/66545
摘要： Provided are methods of manufacturing a semiconductor device. Some embodiments of such methods may include forming a preliminary gate pattern on a substrate. The preliminary gate pattern may include silicon. Methods may include forming an insulation layer pattern on the substrate after forming the preliminary gate pattern. The insulation layer pattern exposes an upper face of the preliminary gate pattern. Methods may include forming a metal layer on the upper face of the preliminary gate pattern via an electroless plating process. Methods may include forming a gate pattern including a metal silicide from a reaction between the preliminary gate pattern and the metal layer by performing a heat treatment process.
摘要翻译：提供制造半导体器件的方法。这种方法的一些实施例可以包括在衬底上形成初步栅极图案。初步栅极图案可以包括硅。方法可以包括在形成初步栅极图案之后在衬底上形成绝缘层图案。绝缘层图案露出初步栅极图案的上表面。方法可以包括通过化学镀处理在预选择栅极图案的上表面上形成金属层。方法可以包括通过进行热处理工艺从预选栅极图案和金属层之间的反应形成包括金属硅化物的栅极图案。

6. 发明申请

US20070281424A1 SEMICONDUCTOR DEVICE AND METHOD OF ITS FORMATION 审中-公开
标题翻译：半导体器件及其形成方法
公开(公告)号：US20070281424A1
公开(公告)日：2007-12-06
申请号：US11750699
申请日：2007-05-18
申请人： Hyun-Su Kim , Dae-Yong Kim , Eun-Ji Jung , Eun-Ok Lee , Byung-Hee Kim , Jong-Ho Yun
发明人： Hyun-Su Kim , Dae-Yong Kim , Eun-Ji Jung , Eun-Ok Lee , Byung-Hee Kim , Jong-Ho Yun
IPC分类号： H01L21/336
CPC分类号： H01L29/66545 , H01L21/28052 , H01L21/28097 , H01L21/823835 , H01L21/823842 , H01L29/517 , H01L29/6653 , H01L29/6659
摘要： In an embodiment a first silicon pattern and a second silicon pattern are formed on a substrate. The second silicon pattern has a lower top surface than the first silicon pattern. A first spacer covering a sidewall of the first silicon pattern is formed and a second spacer covering a sidewall of the second silicon pattern is formed. A silicide process is performed to silicidize the first silicon pattern and the second silicon pattern. Work functions of the first and second silicon patterns can be controlled and optimized by controlling the composition of the first and second silicon patterns.
摘要翻译：在一个实施例中，在衬底上形成第一硅图案和第二硅图案。第二硅图案具有比第一硅图案更低的顶表面。形成覆盖第一硅图案的侧壁的第一间隔物，并且形成覆盖第二硅图案的侧壁的第二间隔物。执行硅化处理以硅化第一硅图案和第二硅图案。可以通过控制第一和第二硅图案的组成来控制和优化第一和第二硅图案的功能。

7. 发明申请

US20060234487A1 Method of forming semiconductor device having stacked transistors 失效
公开(公告)号：US20060234487A1
公开(公告)日：2006-10-19
申请号：US11397448
申请日：2006-04-04
申请人： Hyun-Su Kim , Gil-Heyun Choi , Jong-Ho Yun , Sug-Woo Jung , Eun-Ji Jung
发明人： Hyun-Su Kim , Gil-Heyun Choi , Jong-Ho Yun , Sug-Woo Jung , Eun-Ji Jung
IPC分类号： H01L21/44
CPC分类号： H01L21/28518 , H01L21/76898 , H01L21/8221 , H01L27/0688 , H01L27/11 , H01L27/1108
摘要： There is provided a method of forming a semiconductor device having stacked transistors. When forming a contact hole for connecting the stacked transistors to each other, ohmic layers on the bottom and the sidewall of the common contact hole are separately formed. As a result, the respective ohmic layers are optimally formed to meet requirements or conditions. Accordingly, the contact resistance of the common contact may be minimized so that it is possible to enhance the speed of the semiconductor device.

8. 发明申请

US20060199343A1 Method of forming MOS transistor having fully silicided metal gate electrode 审中-公开
标题翻译：形成具有完全硅化金属栅电极的MOS晶体管的方法
公开(公告)号：US20060199343A1
公开(公告)日：2006-09-07
申请号：US11346607
申请日：2006-02-01
申请人： Sug-Woo Jung , Gil-Heyun Choi , Jong-Ho Yun , Hyun-Su Kim , Eun-Ji Jung
发明人： Sug-Woo Jung , Gil-Heyun Choi , Jong-Ho Yun , Hyun-Su Kim , Eun-Ji Jung
IPC分类号： H01L21/336
CPC分类号： H01L29/7834 , H01L21/28518 , H01L29/665 , H01L29/6656 , H01L29/66636
摘要： A method of fabricating a MOS transistor having a fully silicided metal gate electrode is provided. The method includes forming a gate sacrificial pattern and protrusion regions on the gate pattern and active regions of a semiconductor substrate. The gate sacrificial pattern and the protrusion regions then undergo a silicidation process. A reduced gate pattern is formed by disposing an interlayer-insulating layer on semiconductor substrate having the silicided gate sacrificial pattern and silicided protrusion regions, and planarizing the interlayer-insulating layer. The fully silicided metal gate electrode is then formed by siliciding the reduced gate pattern.
摘要翻译：提供一种制造具有完全硅化金属栅电极的MOS晶体管的方法。该方法包括在半导体衬底的栅极图案和有源区上形成栅极牺牲图案和突起区域。然后，栅极牺牲图案和突起区域经历硅化处理。通过在具有硅化栅牺牲图案和硅化突起区域的半导体衬底上设置层间绝缘层，并平坦化层间绝缘层，形成缩小的栅极图案。然后通过将减小的栅极图案硅化来形成完全硅化金属栅电极。

9. 发明申请

US20130020719A1 MICROELECTRONIC DEVICES INCLUDING THROUGH SILICON VIA STRUCTURES HAVING POROUS LAYERS 审中-公开
标题翻译：包含多孔硅的微电子器件通过具有多孔层的结构
公开(公告)号：US20130020719A1
公开(公告)日：2013-01-24
申请号：US13421388
申请日：2012-03-15
申请人： Eun-Ji Jung , Tsukasa Matsuda , Jongho Yun , Jongjin Lee , Gilheyun Choi , Seung-Wook Choi
发明人： Eun-Ji Jung , Tsukasa Matsuda , Jongho Yun , Jongjin Lee , Gilheyun Choi , Seung-Wook Choi
IPC分类号： H01L23/498
CPC分类号： H01L23/481 , H01L21/7682 , H01L21/76831 , H01L21/76898 , H01L25/0657 , H01L2224/16145 , H01L2224/16225 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06565 , H01L2924/1305 , H01L2924/13091 , H01L2924/15311 , H01L2924/00
摘要： A microelectronic device includes a substrate including a via hole extending therethrough, a porous layer on sidewalls of the via hole, and a conductive via electrode extending through the via hole between the sidewalls thereof. The porous layer includes a plurality of pores therein that reduce a dielectric constant of the porous layer. Related fabrication methods are also discussed.
摘要翻译：微电子器件包括：衬底，其包括贯穿其中的通孔，在通孔的侧壁上的多孔层，以及延伸通过其侧壁之间的通孔的导电通孔电极。多孔层包括其中的多个孔，其减小多孔层的介电常数。还讨论了相关的制造方法。

10. 发明授权

US07998810B2 Methods of forming integrated circuit devices having stacked gate electrodes 有权
标题翻译：形成具有层叠栅电极的集成电路器件的方法
公开(公告)号：US07998810B2
公开(公告)日：2011-08-16
申请号：US12424922
申请日：2009-04-16
申请人： Byung-hee Kim , Gil-heyun Choi , Sang-woo Lee , Chang-won Lee , Jin-ho Park , Eun-ji Jung , Jeong-gil Lee
发明人： Byung-hee Kim , Gil-heyun Choi , Sang-woo Lee , Chang-won Lee , Jin-ho Park , Eun-ji Jung , Jeong-gil Lee
IPC分类号： H01L21/336
CPC分类号： H01L27/11521 , H01L21/28273 , H01L29/66545
摘要： A method of forming a gate electrode of a semiconductor device is provided, the method including: forming a plurality of stacked structures each comprising a tunnel dielectric layer, a first silicon layer for floating gates, an intergate dielectric layer, a second silicon layer for control gates, and a mask pattern, on a semiconductor substrate in the stated order; forming a first interlayer dielectric layer between the plurality of stacked structures so that a top surface of the mask pattern is exposed; selectively removing the mask pattern of which the top surface is exposed; forming a third silicon layer in an area from which the hard disk layer was removed, and forming a silicon layer comprising the third silicon layer and the second silicon layer; recessing the first interlayer dielectric layer so that an upper portion of the silicon layer protrudes over the he first interlayer dielectric layer; and forming a metal silicide layer on the upper portion of the silicon layer.
摘要翻译：提供一种形成半导体器件的栅电极的方法，所述方法包括：形成多个堆叠结构，每个堆叠结构包括隧道介电层，用于浮置栅极的第一硅层，栅极间介电层，用于控制的第二硅层栅极和掩模图案，以所述顺序在半导体衬底上; 在所述多个堆叠结构之间形成第一层间电介质层，使得所述掩模图案的顶表面露出; 选择性地去除其顶表面暴露的掩模图案; 在去除所述硬盘层的区域中形成第三硅层，以及形成包含所述第三硅层和所述第二硅层的硅层; 使第一层间电介质层凹陷，使得硅层的上部突出在第一层间介电层上; 以及在所述硅层的上部形成金属硅化物层。

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