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1. 发明授权

US08643096B2 Semiconductor device with buried bit line and method for fabricating the same 有权
标题翻译：具有掩埋位线的半导体器件及其制造方法
公开(公告)号：US08643096B2
公开(公告)日：2014-02-04
申请号：US13554739
申请日：2012-07-20
申请人： Eui-Seong Hwang
发明人： Eui-Seong Hwang
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119 , H01L21/8238 , H01L21/336
CPC分类号： H01L29/66666 , H01L21/8238 , H01L27/1052 , H01L27/10814 , H01L27/10876 , H01L27/10885 , H01L29/78642
摘要： A semiconductor device includes trenches defined in a substrate, buried bit lines partially filling the trenches, a first source/drain layer filling remaining portions of the trenches on the buried bit lines, stack patterns having a channel layer and a second source/drain layer stacked therein and bonded to the first source/drain layer, wherein the channel layer contacts with the first source/drain layer, and word lines crossing with the buried bit lines and disposed adjacent to sidewalls of the channel layer.
摘要翻译：半导体器件包括限定在衬底中的沟槽，部分地填充沟槽的掩埋位线，填充掩埋位线上的沟槽的剩余部分的第一源极/漏极层，具有沟道层的堆叠图案和堆叠的第二源极/漏极层并且与第一源极/漏极层接合，其中沟道层与第一源极/漏极层接触，以及与掩埋位线交叉并且邻近通道层的侧壁设置的字线。

2. 发明授权

US08860127B2 Vertical channel transistor with self-aligned gate electrode and method for fabricating the same 有权
标题翻译：具有自对准栅电极的垂直沟道晶体管及其制造方法
公开(公告)号：US08860127B2
公开(公告)日：2014-10-14
申请号：US13605550
申请日：2012-09-06
申请人： Heung-Jae Cho , Eui-Seong Hwang , Eun-Shil Park
发明人： Heung-Jae Cho , Eui-Seong Hwang , Eun-Shil Park
IPC分类号： H01L21/28 , H01L29/78
CPC分类号： H01L29/66666 , H01L21/28026 , H01L27/10814 , H01L27/10873 , H01L29/402 , H01L29/407 , H01L29/42356 , H01L29/42376 , H01L29/7827
摘要： A method for fabricating vertical channel transistors includes forming a plurality of pillars which have laterally opposing both sidewalls, over a substrate; forming a gate dielectric layer on both sidewalls of the pillars; forming first gate electrodes which cover any one sidewalls of the pillars and shield gate electrodes which cover the other sidewalls of the pillars and have a height lower than the first gate electrodes, over the gate dielectric layer; and forming second gate electrodes which are connected with upper portions of sidewalls of the first gate electrodes.
摘要翻译：一种用于制造垂直沟道晶体管的方法，包括在衬底上形成横向相对的两个侧壁的多个柱; 在支柱的两个侧壁上形成栅介电层; 形成覆盖所述柱的任何一个侧壁的第一栅电极和覆盖所述柱的其它侧壁并且具有低于所述第一栅电极的高度的屏蔽栅电极; 以及形成与所述第一栅电极的侧壁的上部连接的第二栅电极。

3. 发明申请

US20130320433A1 VERTICAL CHANNEL TRANSISTOR WITH SELF-ALIGNED GATE ELECTRODE AND METHOD FOR FABRICATING THE SAME 有权
公开(公告)号：US20130320433A1
公开(公告)日：2013-12-05
申请号：US13605550
申请日：2012-09-06
申请人： Heung-Jae CHO , Eui-Seong Hwang , Eun-Shil Park
发明人： Heung-Jae CHO , Eui-Seong Hwang , Eun-Shil Park
IPC分类号： H01L21/28 , H01L29/78
CPC分类号： H01L29/66666 , H01L21/28026 , H01L27/10814 , H01L27/10873 , H01L29/402 , H01L29/407 , H01L29/42356 , H01L29/42376 , H01L29/7827
摘要： A method for fabricating vertical channel transistors includes forming a plurality of pillars which have laterally opposing both sidewalls, over a substrate; forming a gate dielectric layer on both sidewalls of the pillars; forming first gate electrodes which cover any one sidewalls of the pillars and shield gate electrodes which cover the other sidewalls of the pillars and have a height lower than the first gate electrodes, over the gate dielectric layer; and forming second gate electrodes which are connected with upper portions of sidewalls of the first gate electrodes.

4. 发明申请

US20130234242A1 SEMICONDUCTOR DEVICE WITH BURIED BIT LINE AND METHOD FOR FABRICATING THE SAME 有权
公开(公告)号：US20130234242A1
公开(公告)日：2013-09-12
申请号：US13554739
申请日：2012-07-20
申请人： Eui-Seong HWANG
发明人： Eui-Seong HWANG
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66666 , H01L21/8238 , H01L27/1052 , H01L27/10814 , H01L27/10876 , H01L27/10885 , H01L29/78642
摘要： A semiconductor device includes trenches defined in a substrate, buried bit lines partially filling the trenches, a first source/drain layer filling remaining portions of the trenches on the buried bit lines, stack patterns having a channel layer and a second source/drain layer stacked therein and bonded to the first source/drain layer, wherein the channel layer contacts with the first source/drain layer, and word lines crossing with the buried bit lines and disposed adjacent to sidewalls of the channel layer.

5. 发明申请

US20120171846A1 METHOD FOR FABRICATING SEMICONDUCTOR DEVICE WITH BURIED BIT LINES 有权
标题翻译：用双绞线制造半导体器件的方法
公开(公告)号：US20120171846A1
公开(公告)日：2012-07-05
申请号：US13153958
申请日：2011-06-06
申请人： Eui-Seong HWANG
发明人： Eui-Seong HWANG
IPC分类号： H01L21/20
CPC分类号： H01L27/10885 , H01L21/743
摘要： A method for fabricating a semiconductor device includes etching a substrate to form trenches that separate active regions, forming an insulation layer having an opening to open a portion of a sidewall of each active region, forming a silicon layer pattern to gap-fill a portion of each trench and cover the opening in the insulation layer, forming a metal layer over the silicon layer pattern, and forming a metal silicide layer as buried bit lines, where the metal silicide layer is formed when the metal layer reacts with the silicon layer pattern.
摘要翻译：一种用于制造半导体器件的方法包括蚀刻衬底以形成分隔有源区的沟槽，形成具有开口的绝缘层，以打开每个有源区的侧壁的一部分，形成硅层图案以间隙填充一部分每个沟槽并且覆盖绝缘层中的开口，在硅层图案上形成金属层，并形成金属硅化物层作为掩埋位线，其中当金属层与硅层图案反应时形成金属硅化物层。

6. 发明申请

US20060024883A1 Method for fabricating semiconductor memory device having cylinder type storage node 失效
公开(公告)号：US20060024883A1
公开(公告)日：2006-02-02
申请号：US11149175
申请日：2005-06-10
申请人： Eui-Seong Hwang
发明人： Eui-Seong Hwang
IPC分类号： H01L21/8242
CPC分类号： H01L28/91 , H01L27/10852
摘要： Disclosed is a method for fabricating a semiconductor memory device capable of preventing a bunker defect caused by a pinhole or a crack on a single metal layer used as a storage node. The method includes the steps of: forming a plurality of storage node plugs on a substrate; forming an insulation layer with a plurality of openings exposing surfaces of the plurality of storage node plugs on the substrate; forming a plurality of cylinder-type storage nodes inside of the plurality of opening in a structure that a different kind of conductive layer is formed between the same kinds of conductive layers; selectively removing the insulation layer; forming a dielectric layer on the plurality of cylinder type storage nodes; and forming a plate electrode on the dielectric layer.

7. 发明授权

US06623799B1 Chemical vapor deposition method using a catalyst on a substrate surface 有权
标题翻译：在衬底表面上使用催化剂的化学气相沉积法
公开(公告)号：US06623799B1
公开(公告)日：2003-09-23
申请号：US09554444
申请日：2000-07-13
申请人： Ji-Hwa Lee , Eui-Seong Hwang
发明人： Ji-Hwa Lee , Eui-Seong Hwang
IPC分类号： C23C1618
CPC分类号： C23C16/44 , C23C16/18
摘要： A method of chemically depositing a copper film in which a bromine or iodine-containing catalyst component is employed to enhance the deposition rate. The present invention is characterized in that the catalyst component floats on the film surface during the film formation. Accordingly, a film deposition having superior step coverage and high deposition rate is obtained.
摘要翻译：一种化学沉积铜膜的方法，其中使用含溴或碘的催化剂组分以提高沉积速率。本发明的特征在于，在成膜期间催化剂组分漂浮在膜表面上。因此，获得具有优异的台阶覆盖率和高沉积速率的薄膜沉积。

8. 发明授权

US08609491B2 Method for fabricating semiconductor device with buried bit lines 有权
标题翻译：具有掩埋位线的半导体器件的制造方法
公开(公告)号：US08609491B2
公开(公告)日：2013-12-17
申请号：US13153958
申请日：2011-06-06
申请人： Eui-Seong Hwang
发明人： Eui-Seong Hwang
IPC分类号： H01L21/336
CPC分类号： H01L27/10885 , H01L21/743
摘要： A method for fabricating a semiconductor device includes etching a substrate to form trenches that separate active regions, forming an insulation layer having an opening to open a portion of a sidewall of each active region, forming a silicon layer pattern to gap-fill a portion of each trench and cover the opening in the insulation layer, forming a metal layer over the silicon layer pattern, and forming a metal silicide layer as buried bit lines, where the metal silicide layer is formed when the metal layer reacts with the silicon layer pattern.
摘要翻译：一种用于制造半导体器件的方法包括蚀刻衬底以形成分隔有源区的沟槽，形成具有开口的绝缘层，以打开每个有源区的侧壁的一部分，形成硅层图案以间隙填充一部分每个沟槽并且覆盖绝缘层中的开口，在硅层图案上形成金属层，并形成金属硅化物层作为掩埋位线，其中当金属层与硅层图案反应时形成金属硅化物层。

9. 发明授权

US07504300B2 Method for fabricating semiconductor memory device having cylinder type storage node 失效
标题翻译：具有圆柱型存储节点的半导体存储器件的制造方法
公开(公告)号：US07504300B2
公开(公告)日：2009-03-17
申请号：US11149175
申请日：2005-06-10
申请人： Eui-Seong Hwang
发明人： Eui-Seong Hwang
IPC分类号： H01L21/8239
CPC分类号： H01L28/91 , H01L27/10852
摘要： Disclosed is a method for fabricating a semiconductor memory device capable of preventing a bunker defect caused by a pinhole or a crack on a single metal layer used as a storage node. The method includes the steps of: forming a plurality of storage node plugs on a substrate; forming an insulation layer with a plurality of openings exposing surfaces of the plurality of storage node plugs on the substrate; forming a plurality of cylinder-type storage nodes inside of the plurality of opening in a structure that a different kind of conductive layer is formed between the same kinds of conductive layers; selectively removing the insulation layer; forming a dielectric layer on the plurality of cylinder type storage nodes; and forming a plate electrode on the dielectric layer.
摘要翻译：公开了一种制造半导体存储器件的方法，该半导体存储器件能够防止在用作存储节点的单个金属层上由针孔或裂纹引起的掩体缺陷。该方法包括以下步骤：在衬底上形成多个存储节点插头; 形成具有多个开口的绝缘层，所述多个开口暴露在所述基板上的所述多个存储节点插塞的表面; 在相同种类的导电层之间形成不同种类的导电层的结构中，在多个开口内部形成多个圆柱型存储节点; 选择性地去除绝缘层; 在所述多个圆筒型存储节点上形成介电层; 以及在所述电介质层上形成平板电极。

10. 发明申请

US20050250321A1 Method for fabricating semiconductor device having diffusion barrier layer 审中-公开
标题翻译：制造具有扩散阻挡层的半导体器件的方法
公开(公告)号：US20050250321A1
公开(公告)日：2005-11-10
申请号：US11020750
申请日：2004-12-21
申请人： Eui-Seong Hwang
发明人： Eui-Seong Hwang
IPC分类号： H01L21/28 , H01L21/285 , H01L21/3205 , H01L21/44 , H01L21/768
CPC分类号： H01L21/76846 , H01L21/28518 , H01L21/28556 , H01L21/32051 , H01L21/76855 , H01L21/76876
摘要： The present invention relates to a method for fabricating a diffusion barrier layer of a semiconductor device. The method includes the steps of: forming an insulation layer a metal interconnection line; etching the insulation layer, thereby forming an opening to expose a portion of the metal interconnection line; forming a soaking layer on the insulation layer and the opening; forming a diffusion barrier layer on the soaking layer; and filling a metal layer into the opening.
摘要翻译：本发明涉及半导体器件的扩散阻挡层的制造方法。该方法包括以下步骤：形成绝缘层金属互连线; 蚀刻绝缘层，从而形成用于暴露金属互连线的一部分的开口; 在绝缘层和开口上形成均热层; 在均热层上形成扩散阻挡层; 并将金属层填充到开口中。

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