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1. 发明申请

US20130137257A1 Method of Forming a Semiconductor Device by Using Sacrificial Gate Electrodes and Sacrificial Self-Aligned Contact Structures 有权
标题翻译：通过使用牺牲栅极电极和牺牲自对准接触结构形成半导体器件的方法
公开(公告)号：US20130137257A1
公开(公告)日：2013-05-30
申请号：US13305131
申请日：2011-11-28
申请人： Andy Wei , Peter Baars , Erik Geiss
发明人： Andy Wei , Peter Baars , Erik Geiss
IPC分类号： H01L21/28
CPC分类号： H01L21/28079 , H01L21/76897 , H01L29/495 , H01L29/517 , H01L29/665 , H01L29/66545
摘要： Disclosed herein are various methods of forming a semiconductor device using sacrificial gate electrodes and sacrificial self-aligned contacts. In one example, the method includes forming two spaced-apart sacrificial gate electrodes comprised of a first material, forming a sacrificial contact structure comprised of a second material, wherein the second material is selectively etchable with respect to said first material, and performing an etching process on the two spaced-apart sacrificial gate electrodes and the sacrificial contact structure to selectively remove the two spaced-apart sacrificial gate electrode structures selectively relative to the sacrificial contact structure.
摘要翻译：本文公开了使用牺牲栅电极和牺牲自对准触点形成半导体器件的各种方法。在一个示例中，该方法包括形成由第一材料构成的两个间隔开的牺牲栅电极，形成包括第二材料的牺牲接触结构，其中第二材料相对于所述第一材料可选择性地蚀刻，并且执行蚀刻在两个间隔开的牺牲栅电极和牺牲接触结构之间进行选择性地相对于牺牲接触结构选择性地去除两个间隔开的牺牲栅极电极结构。

2. 发明授权

US07601641B1 Two step optical planarizing layer etch 有权
标题翻译：两步光学平坦化层蚀刻
公开(公告)号：US07601641B1
公开(公告)日：2009-10-13
申请号：US12059888
申请日：2008-03-31
申请人： Erik Geiss , Christopher Prindle , Sven Beyer
发明人： Erik Geiss , Christopher Prindle , Sven Beyer
IPC分类号： H01L21/302
CPC分类号： H01L21/31144 , H01L21/0271
摘要： Methods are provided for etching during fabrication of a semiconductor device. The method includes initially etching to partially remove a portion of one or more lithographic-aiding layers overlying an oxide layer while etching a first portion of the oxide layer in accordance with a mask formed by the one or more lithographic-aiding layers, and thereafter additionally etching to remove remaining portions of the one or more lithographic-aiding layers while etching a remaining portion of the oxide layer.
摘要翻译：在制造半导体器件期间提供蚀刻方法。该方法包括首先蚀刻以根据由一个或多个平版印刷助剂层形成的掩模蚀刻氧化物层的第一部分而部分地去除覆盖在氧化物层上的一个或多个平版印刷辅助层的一部分，此后另外蚀刻以除去一个或多个平版印刷辅助层的剩余部分，同时蚀刻氧化物层的剩余部分。

3. 发明授权

US08614123B2 Method of forming a semiconductor device by using sacrificial gate electrodes and sacrificial self-aligned contact structures 有权
标题翻译：通过使用牺牲栅电极和牺牲自对准接触结构形成半导体器件的方法
公开(公告)号：US08614123B2
公开(公告)日：2013-12-24
申请号：US13305131
申请日：2011-11-28
申请人： Andy Wei , Peter Baars , Erik Geiss
发明人： Andy Wei , Peter Baars , Erik Geiss
IPC分类号： H01L21/8238
CPC分类号： H01L21/28079 , H01L21/76897 , H01L29/495 , H01L29/517 , H01L29/665 , H01L29/66545
摘要： Disclosed herein are various methods of forming a semiconductor device using sacrificial gate electrodes and sacrificial self-aligned contacts. In one example, the method includes forming two spaced-apart sacrificial gate electrodes comprised of a first material, forming a sacrificial contact structure comprised of a second material, wherein the second material is selectively etchable with respect to said first material, and performing an etching process on the two spaced-apart sacrificial gate electrodes and the sacrificial contact structure to selectively remove the two spaced-apart sacrificial gate electrode structures selectively relative to the sacrificial contact structure.
摘要翻译：本文公开了使用牺牲栅电极和牺牲自对准触点形成半导体器件的各种方法。在一个示例中，该方法包括形成由第一材料构成的两个间隔开的牺牲栅电极，形成包括第二材料的牺牲接触结构，其中第二材料相对于所述第一材料可选择性地蚀刻，并且执行蚀刻在两个间隔开的牺牲栅电极和牺牲接触结构之间进行选择性地相对于牺牲接触结构选择性地去除两个间隔开的牺牲栅极电极结构。

4. 发明申请

US20090246959A1 TWO STEP OPTICAL PLANARIZING LAYER ETCH 有权
标题翻译：两步光学平面层蚀刻
公开(公告)号：US20090246959A1
公开(公告)日：2009-10-01
申请号：US12059888
申请日：2008-03-31
申请人： Erik GEISS , Christopher PRINDLE , Sven BEYER
发明人： Erik GEISS , Christopher PRINDLE , Sven BEYER
IPC分类号： H01L21/308
CPC分类号： H01L21/31144 , H01L21/0271
摘要： Methods are provided for etching during fabrication of a semiconductor device. The method includes initially etching to partially remove a portion of one or more lithographic-aiding layers overlying an oxide layer while etching a first portion of the oxide layer in accordance with a mask formed by the one or more lithographic-aiding layers, and thereafter additionally etching to remove remaining portions of the one or more lithographic-aiding layers while etching a remaining portion of the oxide layer.
摘要翻译：在制造半导体器件期间提供蚀刻方法。该方法包括首先蚀刻以根据由一个或多个平版印刷助剂层形成的掩模蚀刻氧化物层的第一部分而部分地去除覆盖在氧化物层上的一个或多个平版印刷辅助层的一部分，此后另外蚀刻以除去一个或多个平版印刷辅助层的剩余部分，同时蚀刻氧化物层的剩余部分。

5. 发明授权

US08927407B2 Method of forming self-aligned contacts for a semiconductor device 有权
标题翻译：形成用于半导体器件的自对准触点的方法
公开(公告)号：US08927407B2
公开(公告)日：2015-01-06
申请号：US13354739
申请日：2012-01-20
申请人： Peter Baars , Andy Wei , Erik Geiss , Martin Mazur
发明人： Peter Baars , Andy Wei , Erik Geiss , Martin Mazur
IPC分类号： H01L21/28
CPC分类号： H01L21/76897 , H01L29/66545
摘要： Disclosed herein is a method of forming self-aligned contacts for a semiconductor device. In one example, the method includes forming a plurality of spaced-apart sacrificial gate electrodes above a semiconducting substrate, wherein each of the gate electrodes has a gate cap layer positioned on the gate electrode, and performing at least one etching process to define a self-aligned contact opening between the plurality of spaced-apart sacrificial gate electrodes. The method further includes removing the gate cap layers to thereby expose an upper surface of each of the sacrificial gate electrodes, depositing at least one layer of conductive material in said self-aligned contact opening and removing portions of the at least one layer of conductive material that are positioned outside of the self-aligned contact opening to thereby define at least a portion of a self-aligned contact positioned in the self-aligned contact opening.
摘要翻译：本文公开了一种形成用于半导体器件的自对准接触件的方法。在一个示例中，该方法包括在半导体衬底之上形成多个间隔开的牺牲栅电极，其中每个栅电极具有位于栅电极上的栅极帽层，并执行至少一个蚀刻工艺以限定自身在多个间隔开的牺牲栅电极之间的对准接触开口。该方法还包括去除栅极盖层，从而暴露每个牺牲栅电极的上表面，在所述自对准接触开口中沉积至少一层导电材料，并去除至少一层导电材料的部分其定位在自对准接触开口的外侧，从而限定位于自对准接触开口中的自对准接触件的至少一部分。

6. 发明申请

US20130189833A1 Method of Forming Self-Aligned Contacts for a Semiconductor Device 有权
标题翻译：形成半导体器件的自对准触点的方法
公开(公告)号：US20130189833A1
公开(公告)日：2013-07-25
申请号：US13354739
申请日：2012-01-20
申请人： Peter Baars , Andy Wei , Erik Geiss , Martin Mazur
发明人： Peter Baars , Andy Wei , Erik Geiss , Martin Mazur
IPC分类号： H01L21/28
CPC分类号： H01L21/76897 , H01L29/66545
摘要： Disclosed herein is a method of forming self-aligned contacts for a semiconductor device. In one example, the method includes forming a plurality of spaced-apart sacrificial gate electrodes above a semiconducting substrate, wherein each of the gate electrodes has a gate cap layer positioned on the gate electrode, and performing at least one etching process to define a self-aligned contact opening between the plurality of spaced-apart sacrificial gate electrodes. The method further includes removing the gate cap layers to thereby expose an upper surface of each of the sacrificial gate electrodes, depositing at least one layer of conductive material in said self-aligned contact opening and removing portions of the at least one layer of conductive material that are positioned outside of the self-aligned contact opening to thereby define at least a portion of a self-aligned contact positioned in the self-aligned contact opening.
摘要翻译：本文公开了一种形成用于半导体器件的自对准接触件的方法。在一个示例中，该方法包括在半导体衬底之上形成多个间隔开的牺牲栅电极，其中每个栅电极具有位于栅电极上的栅极帽层，并执行至少一个蚀刻工艺以限定自身在多个间隔开的牺牲栅电极之间的对准接触开口。该方法还包括去除栅极盖层，从而暴露每个牺牲栅电极的上表面，在所述自对准接触开口中沉积至少一层导电材料，并去除至少一层导电材料的部分其定位在自对准接触开口的外侧，从而限定位于自对准接触开口中的自对准接触件的至少一部分。

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