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1. 发明授权

US06272067B1 SRAM synchronized with an optimized clock signal based on a delay and an external clock 失效
标题翻译： SRAM与基于延迟和外部时钟的优化时钟信号同步
公开(公告)号：US06272067B1
公开(公告)日：2001-08-07
申请号：US09613927
申请日：2000-07-11
申请人： Bruce C. Sun , Eric W. Lee , Huy Nguyen
发明人： Bruce C. Sun , Eric W. Lee , Huy Nguyen
IPC分类号： G11C800
CPC分类号： G11C7/106 , G11C7/1012 , G11C7/1051 , G11C7/1066 , G11C7/1072 , G11C7/1078 , G11C7/1087 , G11C7/222 , G11C11/419
摘要： A synchronous SRAM chip that can increase the number of times it may be accessed within a single clock cycle. By knowing the processor's clock speed and determining a critical time, a signal optimizer may be constructed. The critical time is the longest interval of time required for a worst-case scenario memory access. A signal optimizer transforms the clock signal into a signal that has a higher frequency than the original clock signal and maintains both its high state and its low state for at least the critical time. By then allowing the synchronous SRAM chip to perform its access and pre-charge during the dips and posts of the optimized clock signal, the synchronous SRAM chip can perform multiple accesses and pre-charges during one clock cycle. The SRAM chip can be used for direct memory accesses such that the processor does not need to arbitrate access to the memory.
摘要翻译：同步SRAM芯片可以增加在单个时钟周期内访问的次数。通过了解处理器的时钟速度并确定关键时间，可以构建信号优化器。关键时间是最坏情况下存储器访问所需的最长时间间隔。信号优化器将时钟信号变换成具有比原始时钟信号更高的频率的信号，并且至少在关键时刻保持其高状态和低状态。在允许同步SRAM芯片在优化的时钟信号的下降和下降期间执行其访问和预充电，同步SRAM芯片可以在一个时钟周期内执行多次访问和预充电。 SRAM芯片可用于直接存储器访问，使得处理器不需要仲裁访问存储器。

2. 发明授权

US06324122B1 RAM synchronized with a signal 失效
标题翻译： RAM与信号同步
公开(公告)号：US06324122B1
公开(公告)日：2001-11-27
申请号：US09835010
申请日：2001-04-13
申请人： Bruce C. Sun , Eric W. Lee , Huy Nguyen
发明人： Bruce C. Sun , Eric W. Lee , Huy Nguyen
IPC分类号： G11C800
CPC分类号： G11C7/106 , G11C7/1012 , G11C7/1051 , G11C7/1066 , G11C7/1072 , G11C7/1078 , G11C7/1087 , G11C7/222 , G11C11/419
摘要： A RAM module that can increase the number of times it may be accessed within a single clock cycle. By knowing the processor's clock speed and determining a critical time, a signal optimizer may be constructed. The critical time is the longest interval of time required for a worst-case scenario memory access. A signal optimizer transforms the clock signal into a signal that has a higher frequency than the original clock signal and maintains both its high state and its low state for at least the critical time. By then allowing the RAM module to perform its access and pre-charge during the dips and posts of the optimized clock signal, the RAM module can perform multiple accesses and pre-charges during one clock cycle. The RAM module can be used for direct memory accesses such that the processor does not need to arbitrate access to the memory.
摘要翻译： RAM模块可以增加在单个时钟周期内访问的次数。通过了解处理器的时钟速度并确定关键时间，可以构建信号优化器。关键时间是最坏情况下存储器访问所需的最长时间间隔。信号优化器将时钟信号变换成具有比原始时钟信号更高的频率的信号，并且至少在关键时刻保持其高状态和低状态。在允许RAM模块在优化的时钟信号的下降和下降期间执行其访问和预充电，RAM模块可以在一个时钟周期内执行多次访问和预充电。 RAM模块可用于直接存储器访问，使得处理器不需要仲裁访问存储器。

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