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1. 发明授权

US06898144B2 Actively driven VREF for input buffer noise immunity 失效
标题翻译：积极驱动VREF，实现输入缓冲器抗干扰能力
公开(公告)号：US06898144B2
公开(公告)日：2005-05-24
申请号：US10624772
申请日：2003-07-22
申请人： Eric T. Stubbs , James E. Miller
发明人： Eric T. Stubbs , James E. Miller
IPC分类号： G11C5/14 , G11C11/34 , G11C7/00
CPC分类号： G11C5/147
摘要： A memory device including a circuit for actively driving a reference voltage in a memory device is disclosed. A circuit integrated in a memory device and coupled to an external voltage source substantially eliminates fluctuations in the reference voltage of the memory device caused by power supply changes and noise occurring in the memory device by generating a constant voltage and good current drive from the external voltage source.
摘要翻译：公开了一种包括用于在存储器件中主动驱动参考电压的电路的存储器件。集成在存储器件中并耦合到外部电压源的电路基本上消除了由存储器件中发生的电源变化和噪声引起的存储器件参考电压的波动，通过从外部电压产生恒定电压和良好的电流驱动资源。

2. 发明授权

US06727739B2 Compensation for a delay locked loop 失效
标题翻译：补偿延时锁定环
公开(公告)号：US06727739B2
公开(公告)日：2004-04-27
申请号：US10054415
申请日：2002-01-22
申请人： Eric T. Stubbs , Christopher K. Morzano
发明人： Eric T. Stubbs , Christopher K. Morzano
IPC分类号： H03L700
CPC分类号： G11C7/1066 , G11C7/1051 , G11C7/22 , G11C7/222 , H03L7/0814 , H03L7/10
摘要： A method and apparatus for compensating a delay locked loop against signal timing variances after circuit initialization which cause delay shifts due to temperature and voltage changes and operational noise. A delay line of a delay locked loop is disclosed, the delay line having a plurality of delay elements and a minimum and maximum delay boundary. According to an embodiment of the invention, an artificial minimum or maximum boundary, or both, is established on the delay line such that during initialization of the delay locked loop circuit, the circuit cannot lock on a delay element beyond the artificial minimum or maximum boundaries. By offsetting the artificial minimum and maximum boundaries from the actual minimum and maximum boundaries of the delay line, a buffer of delay elements is established at the actual delay line boundaries. During operation of the delay locked loop apart from initialization, the artificial boundaries become transparent to the delay locked loop and are available for the circuitry to use if needed.
摘要翻译：一种用于在电路初始化之后补偿延迟锁定环相对于信号定时方差的方法和装置，其导致由于温度和电压变化以及操作噪声引起的延迟移位。延迟锁定环路的延迟线被公开，延迟线具有多个延迟元件和最小和最大延迟边界。根据本发明的实施例，在延迟线上建立人造最小或最大边界或两者，使得在延迟锁定环路电路的初始化期间，电路不能锁定超出人造最小或最大边界的延迟元件。通过将人造最小和最大边界与延迟线的实际最小和最大边界相抵消，延迟元件的缓冲器在实际延迟线边界处被建立。在延迟锁定环路的操作期间，除了初始化之外，仿真边界对于延迟锁定环路变得透明，并且如果需要，可用于电路使用。

3. 发明授权

US06625692B1 Integrated semiconductor memory chip with presence detect data capability 有权
标题翻译：具有存在检测数据能力的集成半导体存储器芯片
公开(公告)号：US06625692B1
公开(公告)日：2003-09-23
申请号：US09291369
申请日：1999-04-14
申请人： Eric T. Stubbs , Gordon D. Roberts
发明人： Eric T. Stubbs , Gordon D. Roberts
IPC分类号： G06F1200
CPC分类号： G06F12/0684
摘要： An integrated semiconductor memory chip includes hardwired presence detect data which can be accessed for transmission to a location external to the memory chip as well as logic allowing additional presence detect data to be programmed in the memory chip after fabrication of the memory chip. Storing the presence detect data on the memory chip rather than on a separate integrated circuit can help reduce the number of integrated chips required for a memory module, which may include multiple DRAM or other memory chips. Hardwiring at least some of the presence detect data during fabrication of the chip can reduce the number of programming errors as well as the number of mismatches that might otherwise occur if a separate presence detect data chip were used. On the other hand, the capability of programming presence detect data after fabrication of the memory chip provides additional flexibility, allowing the foregoing techniques to be used with a wide variety of memory chips and modules.
摘要翻译：集成半导体存储器芯片包括可以存取的硬接线存在检测数据，用于传输到存储器芯片外部的位置，以及允许在存储器芯片制造之后在存储器芯片中编程附加存在检测数据的逻辑。将存在检测数据存储在存储器芯片而不是在单独的集成电路上可以有助于减少存储器模块所需的集成芯片的数量，存储器模块可能包括多个DRAM或其他存储器芯片。在制造芯片期间，至少部分存在检测数据的硬接线可以减少编程错误的数量以及如果使用单独的存在检测数据芯片可能会发生的不匹配的数量。另一方面，在存储芯片制造之后编程存在检测数据的能力提供了额外的灵活性，允许前述技术与各种存储器芯片和模块一起使用。

4. 发明授权

US06259162B1 Method for reducing capactive coupling between conductive lines 失效
标题翻译：减少导线之间的负载耦合的方法
公开(公告)号：US06259162B1
公开(公告)日：2001-07-10
申请号：US09150628
申请日：1998-09-09
申请人： Kin F. Ma , Eric T. Stubbs
发明人： Kin F. Ma , Eric T. Stubbs
IPC分类号： H01L2940
CPC分类号： H01L21/76838 , Y10S257/907
摘要： An embodiment of the present invention discloses a memory device having an array with digit lines arranged in complementary pairs, the array comprising; a substantially planar layer having trenches therein; a first level of digit lines residing at least partially in the trenches; a second level of digit lines residing on the surface of the layer, the second level extending in generally parallel relation to the digit lines in the first level. The first level of digit lines are in alternating positions with the second level of digit lines and the alternating positions comprise a repeating pattern of a first complementary pair of digit lines at the first level adjacent a second complementary pair of digit lines at the second level.
摘要翻译：本发明的一个实施例公开了一种具有排列成互补对的数字线的阵列的存储器件，该阵列包括：其中具有沟槽的基本平坦的层; 至少部分驻留在沟槽中的第一级数字线; 驻留在层的表面上的第二级数字线，第二级与第一级的数字线大致平行地延伸。数字线的第一级与第二级数字线处于交替位置，并且交替位置包括与第二级相邻的第二互补数字线对的第一级处的第一互补数字线对的重复图案。

5. 发明授权

US6011731A Cell plate regulator 失效
标题翻译：电池板调节器
公开(公告)号：US6011731A
公开(公告)日：2000-01-04
申请号：US259221
申请日：1999-03-01
申请人： Kurt D. Beigel , Manny K. Ma , Gordon D. Roberts , James E. Miller , Daryl L. Habersetzer , Jeffrey D. Bruce , Eric T. Stubbs
发明人： Kurt D. Beigel , Manny K. Ma , Gordon D. Roberts , James E. Miller , Daryl L. Habersetzer , Jeffrey D. Bruce , Eric T. Stubbs
IPC分类号： G11C7/00 , G11C29/02 , G11C29/12 , G11C29/44 , G11C29/48 , G11C29/50 , G11C29/56
CPC分类号： G11C29/026 , G11C29/02 , G11C29/025 , G11C29/028 , G11C29/12 , G11C29/44 , G11C29/48 , G11C29/50 , G11C29/50012 , G11C29/56 , G11C11/401 , G11C2029/5004
摘要： As part of a memory array, a circuit is provided for altering the drive applied to an access transistor that regulates electrical communication within the memory array. In one embodiment, the circuit is used to alter the drive applied to a sense amp's voltage-pulling transistor, thereby allowing modification of the voltage-pulling rate for components of the sense amp. A sample of test data is written to the memory array and read several times at varying drive rates in order to determine the sense amp's ability to accommodate external circuitry. In another embodiment, the circuit is used to alter the drive applied to a bleeder device that regulates communication between the digit lines of the memory array and its cell plate. Slowing said communication allows defects within the memory array to have a more pronounced effect and hence increases the chances of finding such defects during testing. The circuit is configured to accept and apply a plurality of voltages, either through a contact pad or from a series of discrete voltage sources coupled to the circuit.
摘要翻译：作为存储器阵列的一部分，提供了用于改变施加到调节存储器阵列内的电通信的存取晶体管的驱动电路的电路。在一个实施例中，该电路用于改变施加到感测放大器的电压 - 牵引晶体管的驱动，从而允许改变感测放大器部件的电压提升率。将测试数据的样本写入存储器阵列，并以变化的驱动速率读取数次，以便确定感测放大器容纳外部电路的能力。在另一个实施例中，电路用于改变施加到泄放装置的驱动，其调节存储器阵列的数字线与其单元板之间的通信。减轻所述通信允许存储器阵列中的缺陷具有更显着的效果，并因此增加在测试期间发现这些缺陷的机会。电路被配置为通过接触焊盘或耦合到电路的一系列离散电压源来接受和施加多个电压。

6. 发明授权

US07274605B2 Per-bit set-up and hold time adjustment for double-data rate synchronous DRAM 有权
标题翻译：双数据速率同步DRAM的每位设置和保持时间调整
公开(公告)号：US07274605B2
公开(公告)日：2007-09-25
申请号：US11459684
申请日：2006-07-25
申请人： Eric T. Stubbs
发明人： Eric T. Stubbs
IPC分类号： G11C7/22 , G11C7/10
CPC分类号： G11C7/1087 , G11C7/1078 , G11C7/1084 , G11C2207/107 , G11C2207/2254
摘要： A synchronous double-data-rate semiconductor memory device is adapted to receive write data on both the rising and falling edges of a data strobe signal derived from an externally-applied system clock. In the write path circuitry for each data pin of the device, adjustable delay elements are provided to enable the adjustment of the setup and hold times of write data applied to the data pin relative to the data strobe signal. The delays are separately adjustable for data present during the rising edge of the data strobe signal and for data present during the falling edge of the data strobe signal. The setup and hold window for write data is thus optimizable on a per-bit basis rather than a per-cycle basis. In one embodiment, a delay circuit is provided for generating delaying the rising edge data and the falling edge data by different delay intervals.
摘要翻译：同步双数据速率半导体存储器件适于在从外部施加的系统时钟导出的数据选通信号的上升沿和下降沿两者上接收写入数据。在器件的每个数据引脚的写入路径电路中，提供可调节的延迟元件以使得能够调整相对于数据选通信号施加到数据引脚的写入数据的建立和保持时间。对于在数据选通信号的上升沿期间存在的数据以及在数据选通信号的下降沿期间存在的数据，这些延迟可以单独调节。因此，写入数据的建立和保持窗口可以在每个位的基础上而不是每个周期的基础上进行优化。在一个实施例中，提供延迟电路用于通过不同的延迟间隔产生延迟上升沿数据和下降沿数据。

7. 发明授权

US06862224B2 System and method for operating a memory array 有权
标题翻译：用于操作存储器阵列的系统和方法
公开(公告)号：US06862224B2
公开(公告)日：2005-03-01
申请号：US10660566
申请日：2003-09-12
申请人： Eric T. Stubbs
发明人： Eric T. Stubbs
IPC分类号： G11C7/10 , G11C7/00
CPC分类号： G11C7/106 , G11C7/1039 , G11C7/1051 , G11C2207/107
摘要： A method and apparatus for storing and retrieving data in a second, or higher, order prefetch architecture memory integrated circuit. The method includes storing multiple bits of data in memory cells at various electrical distances from an output buffer and retrieving those memory bits concurrently for output. By outputting the bits in a fixed burst order, according to which a bit from a memory cell closer to the output buffer is output before a bit from a memory cell farther from the output buffer, the output time of the data bit from the closer memory cell can be used to mask a portion of the transit time of the bit from the farther memory cell. The apparatus includes memory cells at various locations for storing data bits, an address decoder adapted to store and retrieve multiple bits in a fixed burst order, and a multiplexer.
摘要翻译：一种用于在第二或更高级订单预取架构存储器集成电路中存储和检索数据的方法和装置。该方法包括将多个位的数据存储在与输出缓冲器不同的电距离的存储器单元中，并且同时检索那些存储器位以用于输出。通过以固定的突发顺序输出比特，根据该比特，来自更靠近输出缓冲器的存储器单元的比特从输出缓冲器之外的存储单元的比特之前输出，数据比特的输出时间从较近的存储器可以使用单元来掩蔽来自更远的存储单元的位的传送时间的一部分。该装置包括用于存储数据位的各个位置处的存储单元，适于以固定突发顺序存储和检索多个位的地址解码器以及多路复用器。

8. 发明授权

US06838712B2 Per-bit set-up and hold time adjustment for double-data rate synchronous DRAM 失效
标题翻译：双数据速率同步DRAM的每位设置和保持时间调整
公开(公告)号：US06838712B2
公开(公告)日：2005-01-04
申请号：US09994205
申请日：2001-11-26
申请人： Eric T. Stubbs
发明人： Eric T. Stubbs
IPC分类号： G11C7/10 , H01L29/73
CPC分类号： G11C7/1087 , G11C7/1078 , G11C7/1084 , G11C2207/107 , G11C2207/2254
摘要： A synchronous double-data-rate semiconductor memory device is adapted to receive write data on both the rising and falling edges of a data strobe signal derived from an externally-applied system clock. In the write path circuitry for each data pin of the device, adjustable delay elements are provided to enable the adjustment of the setup and hold times of write data applied to the data pin relative to the data strobe signal. The delays are separately adjustable for data present during the rising edge of the data strobe signal and for data present during the falling edge of the data strobe signal. The setup and hold window for write data is thus optimizable on a per-bit basis rather than a per-cycle basis. In one embodiment, a delay circuit is provided for generating delaying the rising edge data and the falling edge data by different delay intervals.
摘要翻译：同步双数据速率半导体存储器件适于在从外部施加的系统时钟导出的数据选通信号的上升沿和下降沿两者上接收写入数据。在器件的每个数据引脚的写入路径电路中，提供可调节的延迟元件以使得能够调整相对于数据选通信号施加到数据引脚的写入数据的建立和保持时间。对于在数据选通信号的上升沿期间存在的数据以及在数据选通信号的下降沿期间存在的数据，这些延迟可以单独调节。因此，写入数据的建立和保持窗口可以在每个位的基础上而不是每个周期的基础上进行优化。在一个实施例中，提供延迟电路用于通过不同的延迟间隔产生延迟上升沿数据和下降沿数据。

9. 发明授权

US06791381B2 Method and apparatus for reducing the lock time of a DLL 有权
标题翻译：减少DLL锁定时间的方法和装置
公开(公告)号：US06791381B2
公开(公告)日：2004-09-14
申请号：US10050986
申请日：2002-01-18
申请人： Eric T. Stubbs , James E. Miller
发明人： Eric T. Stubbs , James E. Miller
IPC分类号： H03L706
CPC分类号： H03L7/10 , G06F1/10 , H03L7/0814
摘要： A delay locked loop having improved synchronization times has a variably adjustable delay line which accepts two incoming clock pulses. As each pulse propagates through the delay line an edge of the pulse toggles or retoggles a shift bit corresponding to a delay element. When the first pulse reaches the end of the delay line, the status of the shift bits is frozen, and a starting point for a synchronization sequence begins at the transition point between toggled and retoggled shift bits.
摘要翻译：具有改善的同步时间的延迟锁定环具有可变地调节的延迟线，其接受两个输入时钟脉冲。当每个脉冲通过延迟线传播时，脉冲的边缘切换或重新切换对应于延迟元件的移位位。当第一个脉冲到达延迟线的末端时，移位位的状态被冻结，并且同步序列的起始点在切换和切换移位位之间的转换点处开始。

10. 发明授权

US06667911B2 High speed memory architecture 有权
标题翻译：高速内存架构
公开(公告)号：US06667911B2
公开(公告)日：2003-12-23
申请号：US09973860
申请日：2001-10-11
申请人： Eric T. Stubbs
发明人： Eric T. Stubbs
IPC分类号： G11C700
CPC分类号： G11C7/106 , G11C7/1039 , G11C7/1051 , G11C2207/107
摘要： A method and apparatus for storing and retrieving data in a second, or higher, order prefetch architecture memory integrated circuit. The method includes storing multiple bits of data in memory cells at various electrical distances from an output buffer and retrieving those memory bits concurrently for output. By outputting the bits in a fixed burst order, according to which a bit from a memory cell closer to the output buffer is output before a bit from a memory cell farther from the output buffer, the output time of the data bit from the closer memory cell can be used to mask a portion of the transit time of the bit from the farther memory cell. The apparatus includes memory cells at various locations for storing data bits, an address decoder adapted to store and retrieve multiple bits in a fixed burst order, and a multiplexer.
摘要翻译：一种用于在第二或更高级订单预取架构存储器集成电路中存储和检索数据的方法和装置。该方法包括将多个位的数据存储在与输出缓冲器不同的电距离的存储器单元中，并且同时检索那些存储器位以用于输出。通过以固定的突发顺序输出比特，根据该比特，来自更靠近输出缓冲器的存储器单元的比特从输出缓冲器之外的存储单元的比特之前输出，数据比特的输出时间从较近的存储器可以使用单元来掩蔽来自更远的存储单元的位的传送时间的一部分。该装置包括用于存储数据位的各个位置处的存储单元，适于以固定突发顺序存储和检索多个位的地址解码器以及多路复用器。

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