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1. 发明授权

US08835218B2 Stackable layer containing ball grid array package 有权
标题翻译：可堆叠层包含球栅阵列封装
公开(公告)号：US08835218B2
公开(公告)日：2014-09-16
申请号：US13181221
申请日：2011-07-12
申请人： Keith Gann , W. Eric Boyd
发明人： Keith Gann , W. Eric Boyd
IPC分类号： H01L21/44 , H01L25/10 , H01L23/13 , H01L23/498 , H01L23/00
CPC分类号： H01L23/49805 , H01L23/13 , H01L23/49838 , H01L24/48 , H01L24/73 , H01L25/105 , H01L2224/16225 , H01L2224/32225 , H01L2224/48227 , H01L2224/4824 , H01L2224/73215 , H01L2224/73265 , H01L2225/1023 , H01L2225/1064 , H01L2924/00011 , H01L2924/00014 , H01L2924/01055 , H01L2924/01078 , H01L2924/14 , H01L2924/3011 , H01L2924/00 , H01L2924/00012 , H01L2224/0401 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： Layers suitable for stacking in three dimensional, multi-layer modules are formed by interconnecting a ball grid array electronic package to an interposer layer which routes electronic signals to an access plane. The layers are under-filled and may be bonded together to form a stack of layers. The leads on the access plane are interconnected among layers to form a high-density electronic package.
摘要翻译：通过将球栅阵列电子封装互连到将电子信号路由到接入平面的插入层来形成适于堆叠在三维多层模块中的层。这些层被填充不足并且可以结合在一起以形成一叠层。接入平面上的引线在层之间互连以形成高密度电子封装。

2. 发明授权

US08637140B2 Method for defining an electrically conductive metal structure on a three-dimensional element and a device made from the method 有权
标题翻译：用于在三维元件上限定导电金属结构的方法和由该方法制成的器件
公开(公告)号：US08637140B2
公开(公告)日：2014-01-28
申请号：US13267651
申请日：2011-10-06
申请人： James Yamaguchi , W. Eric Boyd
发明人： James Yamaguchi , W. Eric Boyd
IPC分类号： B32B3/00 , G03F7/20
CPC分类号： B32B15/16 , B32B2559/00
摘要： A method for defining an electrically conductive metalized structure, which may comprise an electrode or trace, on the surface of a three-dimensional element. The three-dimensional element may comprise a glass microsphere or shell resonator. A laser direct write grayscale photolithographic process is used in conjunction with electrically conductive metal deposition processes to define one or more electrically conductive metal structures on the surfaces of the three dimensional element.
摘要翻译：一种用于在三维元件的表面上限定可以包括电极或迹线的导电金属化结构的方法。三维元件可以包括玻璃微球或壳谐振器。激光直写式灰度光刻工艺与导电金属沉积工艺结合使用以在三维元件的表面上限定一个或多个导电金属结构。

3. 发明申请

US20120205801A1 Anti-Tamper Wrapper Interconnect Method and a Device 有权
标题翻译：防篡改包裹互连方法和设备
公开(公告)号：US20120205801A1
公开(公告)日：2012-08-16
申请号：US13370381
申请日：2012-02-10
申请人： Randy Bindrup , James Yamaguchi , W. Eric Boyd
发明人： Randy Bindrup , James Yamaguchi , W. Eric Boyd
IPC分类号： H01L23/498 , B32B37/12
CPC分类号： H01L23/57 , H01L24/17 , H05K1/0275 , H05K3/321 , H05K3/4015
摘要： A method for electrically coupling an anti-tamper mesh to an electronic module or device using wire bonding equipment and a device made from the method. Stud bumps or free air ball bonds are electrically coupled to conductive mesh pads of an anti-tamper mesh. Respective module pads have a conductive epoxy disposed thereon for the receiving of the stud bumps or free air ball bonds, each of which are aligned and bonded together to electrically couple the anti-tamper mesh to predetermined module pads.
摘要翻译：一种使用引线接合设备和由该方法制造的器件将防篡改网电连接到电子模块或设备的方法。螺柱凸起或自由气球接合电耦合到防篡改网的导电网垫。相应的模块焊盘具有设置在其上的导电环氧树脂，用于接收柱形凸块或自由空气球接合，每个凸起对准并结合在一起以将防篡改网电耦合到预定的模块焊盘。

4. 发明申请

US20120068333A1 Wire Bond Through-Via Structure and Method 有权
标题翻译：电线键合通孔结构和方法
公开(公告)号：US20120068333A1
公开(公告)日：2012-03-22
申请号：US13209898
申请日：2011-08-15
申请人： Randy Bindrup , W. Eric Boyd , John Leon , James Yamaguchi
发明人： Randy Bindrup , W. Eric Boyd , John Leon , James Yamaguchi
IPC分类号： H01L23/488 , H01L21/56
CPC分类号： H01L24/45 , H01L21/568 , H01L23/498 , H01L23/49811 , H01L24/05 , H01L24/24 , H01L24/82 , H01L24/96 , H01L25/105 , H01L2224/04042 , H01L2224/45144 , H01L2224/45541 , H01L2224/82001 , H01L2224/96 , H01L2225/1035 , H01L2225/1041 , H01L2225/1052 , H01L2924/00013 , H01L2924/00014 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H01L2924/014 , H01L2924/10253 , H01L2924/14 , H01L2924/15311 , H01L2924/18162 , H01L2924/19107 , H01L2924/3011 , H01L2224/82 , H01L2224/13099 , H01L2224/13599 , H01L2224/05599 , H01L2224/05099 , H01L2224/29099 , H01L2224/29599 , H01L2924/00 , H01L2224/48
摘要： A stackable integrated circuit chip layer and module device that avoids the use of electrically conductive elements on the external surfaces of a layer containing an integrated circuit die by taking advantage of conventional wire bonding equipment to provide an electrically conductive path defined by a wire bond segment that is encapsulated in a potting material so as to define an electrically conductive wire bond “through-via” accessible from at least the lower or second surface of the layer.
摘要翻译：一种可堆叠的集成电路芯片层和模块装置，其避免了在包含集成电路管芯的层的外表面上使用导电元件，利用常规引线键合设备来提供由引线键合段限定的导电路径，封装在灌封材料中，以便限定可从该层的至少下表面或第二表面接近的导电引线键合“通孔”。

5. 发明授权

US07982300B2 Stackable layer containing ball grid array package 有权
标题翻译：可堆叠层包含球栅阵列封装
公开(公告)号：US07982300B2
公开(公告)日：2011-07-19
申请号：US12731970
申请日：2010-03-25
申请人： Keith Gann , W. Eric Boyd
发明人： Keith Gann , W. Eric Boyd
IPC分类号： H01L23/48 , H01L23/02
CPC分类号： H01L23/49805 , H01L23/13 , H01L23/49838 , H01L24/48 , H01L24/73 , H01L25/105 , H01L2224/16225 , H01L2224/32225 , H01L2224/48227 , H01L2224/4824 , H01L2224/73215 , H01L2224/73265 , H01L2225/1023 , H01L2225/1064 , H01L2924/00011 , H01L2924/00014 , H01L2924/01055 , H01L2924/01078 , H01L2924/14 , H01L2924/3011 , H01L2924/00 , H01L2924/00012 , H01L2224/0401 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： Layers suitable for stacking in three dimensional, multi-layer modules are formed by interconnecting a ball grid array electronic package to an interposer layer which routes electronic signals to an access plane. The layers are under-filled and may be bonded together to form a stack of layers. The leads on the access plane are interconnected among layers to form a high-density electronic package.
摘要翻译：通过将球栅阵列电子封装互连到将电子信号路由到接入平面的插入层来形成适于堆叠在三维多层模块中的层。这些层被填充不足并且可以结合在一起以形成一叠层。接入平面上的引线在层之间互连以形成高密度电子封装。

6. 发明申请

US20110031749A1 Energy harvesting buoy 有权
标题翻译：能量采集浮标
公开(公告)号：US20110031749A1
公开(公告)日：2011-02-10
申请号：US12806124
申请日：2010-08-04
申请人： Itzhak Sapir , W. Eric Boyd
发明人： Itzhak Sapir , W. Eric Boyd
IPC分类号： F03B13/16 , H02J7/32
CPC分类号： F03B13/20 , Y02E10/38
摘要： An energy-harvesting buoy is provided comprising an air-pressure generator, such as a piezo-electric generator, or any other generator that can harvest energy from an air pressure. The energy harvesting buoy consists of a first float and a second float. An air pressure is created when relative vertical motion occurs between the first float and the second float which drives an air pressurization means such as a piston driven air pump using a linkage member pivotably mounted between the respective floats. The generator uses the air pressure from the air pressurization means to drive the generator to generate electrical power.
摘要翻译：提供了一种能量收集浮标，其包括诸如压电发生器的空气压力发生器或可以从空气压力收集能量的任何其它发电机。能量收集浮标由第一个浮子和第二个浮子组成。当在第一浮子和第二浮子之间发生相对垂直运动时产生空气压力，该第二浮子利用可枢转地安装在各浮子之间的连杆构件来驱动空气加压装置，例如活塞驱动的空气泵。发电机使用来自空气加压装置的空气压力来驱动发电机产生电力。

7. 发明申请

US20100291735A1 STACKABLE SEMICONDUCTOR CHIP LAYER COMPRISING PREFABRICATED TRENCH INTERCONNECT VIAS 审中-公开
标题翻译：包含预制TRENCH INTERCONNECT VIAS的可堆叠半导体芯片层
公开(公告)号：US20100291735A1
公开(公告)日：2010-11-18
申请号：US12844555
申请日：2010-07-27
申请人： Volkan Ozguz , Angel Pepe , James Yamaguchi , W. Eric Boyd , Douglas Albert , Andrew Camien
发明人： Volkan Ozguz , Angel Pepe , James Yamaguchi , W. Eric Boyd , Douglas Albert , Andrew Camien
IPC分类号： H01L21/70 , H01L21/60
CPC分类号： H01L21/76898 , H01L23/481 , H01L24/02 , H01L25/0657 , H01L2225/06513 , H01L2225/06524 , H01L2225/06541 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01082 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105 , H01L2924/30107 , H01L2924/00
摘要： A stackable layer and stacked multilayer module are disclosed. Individual integrated circuit die are tested and processed at the wafer level to create vertical area interconnect vias for the routing of electrical signals from the active surface of the die to the inactive surface. Vias are formed at predefined locations on each die on the wafer at the reticle level using a series of semiconductor processing steps. The wafer is passivated and the vias are filled with a conductive material. The bond pads on the die are exposed and a metallization reroute from the user-selected bond pads and vias is applied. The wafer is then segmented to form thin, stackable layers that can be stacked and vertically electrically interconnected using the conductive vias, forming high-density electronic modules which may, in turn, be further stacked and interconnected to form larger more complex stacks.
摘要翻译：公开了一种可堆叠层和堆叠多层模块。单个集成电路裸片在晶片级进行测试和处理，以创建用于将电信号从芯片的有源表面路由到非活动表面的垂直区域互连通孔。使用一系列半导体处理步骤，在掩模版级上在晶片上的每个管芯上的预定位置处形成通孔。晶片被钝化，并且通孔填充有导电材料。裸片上的接合焊盘被暴露，并且应用来自用户选择的接合焊盘和通孔的金属化重新路由。然后将晶片分段以形成薄的可堆叠层，其可以使用导电通孔堆叠并垂直电互连，形成高密度电子模块，其可以进一步堆叠并互连以形成更大的更复杂的堆叠。

8. 外观设计

USD591903S1 Cosmetic applicator 有权
公开(公告)号：USD591903S1
公开(公告)日：2009-05-05
申请号：US29323867
申请日：2008-09-02
申请人： Murphy Greene Mongeon , Michael Eric Boyd , Graham Clive Hufton , Ian Andrew Carnduff
设计人： Murphy Greene Mongeon , Michael Eric Boyd , Graham Clive Hufton , Ian Andrew Carnduff

9. 外观设计

USD591512S1 Cosmetic applicator 有权
公开(公告)号：USD591512S1
公开(公告)日：2009-05-05
申请号：US29323865
申请日：2008-09-02
申请人： Murphy Greene Mongeon , Michael Eric Boyd , Graham Clive Hufton , Ian Andrew Carnduff
设计人： Murphy Greene Mongeon , Michael Eric Boyd , Graham Clive Hufton , Ian Andrew Carnduff

10. 发明授权

US07335576B2 Method for precision integrated circuit die singulation using differential etch rates 有权
标题翻译：使用差分蚀刻速率的精密集成电路芯片分离方法
公开(公告)号：US07335576B2
公开(公告)日：2008-02-26
申请号：US11197828
申请日：2005-08-05
申请人： Ludwig David , James Yamaguchi , Stuart Clark , W. Eric Boyd
发明人： Ludwig David , James Yamaguchi , Stuart Clark , W. Eric Boyd
IPC分类号： H01L21/00
CPC分类号： H01L21/78 , H01L21/3065 , H01L21/30655
摘要： A preprocessed semiconductor substrate such as a wafer is provided with a metal etch mask which defines singulation channels on the substrate surface. An isotropic etch process is used to define a singulation channel with a first depth extending into the semiconductor substrate material. A second anisotropic etch process is used to increase the depth of the singulation channel while providing substantially vertical singulation channel sidewalls. The singulation channel can be extended through the depth of the substrate or, in an alternative embodiment, a predetermined portion of the inactive surface of the substrate removed to expose the singulation channels. In this manner, semiconductor die can be precisely singulated from a wafer while maintaining vertical die sidewalls.
摘要翻译：诸如晶片的预处理半导体衬底设置有在衬底表面上限定单个通道的金属蚀刻掩模。使用各向同性蚀刻工艺来限定具有延伸到半导体衬底材料中的第一深度的分离通道。使用第二种各向异性蚀刻工艺来增加单个通道的深度，同时提供基本垂直的分割通道侧壁。分离通道可以延伸穿过衬底的深度，或者在替代实施例中，去除衬底的非活性表面的预定部分以暴露单个通道。以这种方式，可以在保持垂直管芯侧壁的同时从晶片精确地分离半导体管芯。

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