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1. 发明申请

US20070257272A1 Multi-element LED lamp package 有权
标题翻译：多元LED灯具包装
公开(公告)号：US20070257272A1
公开(公告)日：2007-11-08
申请号：US11416804
申请日：2006-05-03
申请人： Edward Hutchins
发明人： Edward Hutchins
IPC分类号： H01L33/00
CPC分类号： F21S48/1705 , F21S41/143 , F21S41/147 , F21S41/321 , F21S41/337 , F21S41/60 , F21S41/663 , F21V7/04 , H01L25/0753 , H01L33/54 , H01L33/60 , H01L2224/48091 , H01L2224/48247 , H01L2224/73265 , H01L2224/8592 , H01L2924/00014 , H01L2924/00
摘要： In one embodiment, a single light emitting diode lamp package includes at least two light emitting devices that can be switched independently of one another and thus may be useful in vehicular lighting applications, for example low and high beam headlights. In another embodiment, a LED device includes a first LED die and at least one additional LED die disposed at different positions within a common reflector cup. Multiple LED sub-assemblies may be mounted to a common lead frame along non-coincident principal axes. Methods for varying intensity or color from multi-LED lamps are further provided.
摘要翻译：在一个实施例中，单个发光二极管灯封装包括至少两个可以彼此独立地切换的发光器件，因此可用于车辆照明应用中，例如低光束和高光束前灯。在另一个实施例中，LED器件包括第一LED管芯和设置在公共反射杯内的不同位置处的至少一个附加LED管芯。多个LED子组件可以沿着不重合的主轴安装到公共引线框架。还提供了用于改变来自多LED灯的强度或颜色的方法。

2. 发明申请

US20060289891A1 Electronic and/or optoelectronic devices grown on free-standing GaN substrates with GaN spacer structures 审中-公开
标题翻译：在具有GaN间隔结构的独立GaN衬底上生长的电子和/或光电子器件
公开(公告)号：US20060289891A1
公开(公告)日：2006-12-28
申请号：US11168501
申请日：2005-06-28
申请人： Edward Hutchins
发明人： Edward Hutchins
IPC分类号： H01L33/00
CPC分类号： H01L33/06 , B82Y20/00 , H01L29/2003 , H01L29/66462 , H01L33/32
摘要： A GaN-based electronic and/or optoelectronic device formed on a free-standing GaN substrate, wherein a thick GaN spacer layer is provided between the device and the substrate, thereby separating the active region of the electronic and/or optoelectronic device from high impurity content at the substrate-epitaxial interface and reducing the detrimental impact of such interfacial impurity on the performance of the electronic and/or optoelectronic device. The GaN spacer layer has a thickness of at least about 0.5 microns, and preferably from about 0.5 micron to about 2 microns.
摘要翻译：形成在独立的GaN衬底上的GaN基电子和/或光电子器件，其中在器件和衬底之间提供厚的GaN间隔层，从而将电子和/或光电子器件的有源区与高杂质分离内容物，并减少这种界面杂质对电子和/或光电子器件的性能的不利影响。 GaN间隔层具有至少约0.5微米，优选约0.5微米至约2微米的厚度。

3. 发明申请

US20060007234A1 Coincident graphics pixel scoreboard tracking system and method 审中-公开
标题翻译：一致的图形像素记分板跟踪系统和方法
公开(公告)号：US20060007234A1
公开(公告)日：2006-01-12
申请号：US10846208
申请日：2004-05-14
申请人： Edward Hutchins , Brian Angell , Jim Battle , Paul Kim
发明人： Edward Hutchins , Brian Angell , Jim Battle , Paul Kim
IPC分类号： G06T1/20 , G09G5/36
CPC分类号： G06T15/005
摘要： Processing pixels in a graphics pipeline. Screen coincidence between a first pixel and a second pixel in a graphics pipeline is detected, wherein the first pixel has entered a downstream pipeline portion of the graphics pipeline but has not yet completed processing within the graphics pipeline. In response to detecting the coincidence, propagation of the second pixel to the downstream pipeline portion is stalled until the first pixel completes processing within the graphics pipeline. A data cache associated with the data fetch stage is invalidated in advance of a data fetch stage of the downstream pipeline portion obtaining data for the second pixel.
摘要翻译：处理图形管道中的像素。检测图形流水线中的第一像素和第二像素之间的屏幕重合，其中第一像素已进入图形流水线的下游流水线部分，但尚未完成图形流水线内的处理。响应于检测到重合，第二像素到下游流水线部分的传播被停止，直到第一像素在图形流水线内完成处理。与数据获取级相关联的数据高速缓存在下游流水线部分的数据获取级之前无效，获得第二像素的数据。

4. 发明申请

US20050253862A1 Data format for low power programmable processor 有权
标题翻译：低功耗可编程处理器的数据格式
公开(公告)号：US20050253862A1
公开(公告)日：2005-11-17
申请号：US10846110
申请日：2004-05-14
申请人： Edward Hutchins , Brian Angell
发明人： Edward Hutchins , Brian Angell
IPC分类号： G09G5/00
CPC分类号： G06F9/30025 , G06F9/30014 , G06T1/20
摘要： A graphics processor includes programmable arithmetic logic units (ALUs) for performing scalar arithmetic operations on pixel packets. For a selected scalar arithmetic operation, operands in pixel packets may be formatted in a S1.8 format to improve dynamic range. For at least one other scalar arithmetic operation, the pixel packets may be formatted in a different data format.
摘要翻译：图形处理器包括用于对像素分组执行标量算术运算的可编程算术逻辑单元（ALU）。对于所选的标量算术运算，像素分组中的操作数可以以S1.8格式格式化，以提高动态范围。对于至少一个其他标量算术运算，像素分组可以被格式化为不同的数据格式。

5. 发明申请

US20050253856A1 Auto software configurable register address space for low power programmable processor 有权
标题翻译：自动软件可配置的寄存器地址空间用于低功耗可编程处理器
公开(公告)号：US20050253856A1
公开(公告)日：2005-11-17
申请号：US10846106
申请日：2004-05-14
申请人： Edward Hutchins , Brian Angell
发明人： Edward Hutchins , Brian Angell
IPC分类号： G06T1/20 , G06T15/00
CPC分类号： G06T15/005
摘要： A configurable graphics pipeline has more than one possible process flow of pixel packets through elements of the graphics pipeline. In one embodiment, a data packet triggers an element of the graphics pipeline to discover an identifier.
摘要翻译：可配置的图形流水线通过图形流水线的元素具有多个可能的像素数据包流程。在一个实施例中，数据分组触发图形流水线的元素以发现标识符。

6. 发明申请

US20050253855A1 Statistics instrumentation for low power programmable processor 有权
标题翻译：低功耗可编程处理器统计仪表
公开(公告)号：US20050253855A1
公开(公告)日：2005-11-17
申请号：US10845714
申请日：2004-05-14
申请人： Edward Hutchins , Brian Angell
发明人： Edward Hutchins , Brian Angell
IPC分类号： G06T1/20 , G06T15/00
CPC分类号： G06T15/005
摘要： A graphics processor includes a graphics pipeline having a set of tap points. A configurable test point selector monitors a selected subset of tap points and counts statistics for at least one condition associated with each tap point of the subset of tap points.
摘要翻译：图形处理器包括具有一组抽头点的图形管线。可配置的测试点选择器监视所选择的抽头子集，并对与抽头点子集的每个抽头点相关联的至少一个条件进行统计。

7. 发明授权

US06657635B1 Binning flush in graphics data processing 有权
标题翻译：在图形数据处理中进行分组
公开(公告)号：US06657635B1
公开(公告)日：2003-12-02
申请号：US09654104
申请日：2000-08-31
申请人： Edward Hutchins , Ming Benjamin Zhu , Sanjay O. Gupta , Scott C. Heeschen , Benjamin J. Garlick
发明人： Edward Hutchins , Ming Benjamin Zhu , Sanjay O. Gupta , Scott C. Heeschen , Benjamin J. Garlick
IPC分类号： G06F1202
CPC分类号： G06T15/00 , G06T1/60
摘要： Methods and systems for optimizing graphics data processing employ various binning flush algorithms to optimize the utilization of binning memory in a graphics system. Binning flush algorithms provide for processing all geometry and commands binned up to the point the binning memory becomes unavailable, and storing and restoring all necessary intermediate data generated during the partial tile rendering.
摘要翻译：用于优化图形数据处理的方法和系统采用各种分组刷新算法来优化图形系统中分箱存储器的利用。分组刷新算法提供了处理所有几何和命令，直到分箱存储器变得不可用，以及存储和恢复在部分磁贴渲染期间生成的所有必要的中间数据。

8. 发明申请

US20060278891A1 Highly uniform group III nitride epitaxial layers on 100 millimeter diameter silicon carbide substrates 有权
标题翻译：在100毫米直径的碳化硅衬底上高度均匀的III族氮化物外延层
公开(公告)号：US20060278891A1
公开(公告)日：2006-12-14
申请号：US11149664
申请日：2005-06-10
申请人： Adam Saxler , Edward Hutchins
发明人： Adam Saxler , Edward Hutchins
IPC分类号： H01L31/00
CPC分类号： C30B29/36 , C30B29/403 , C30B29/406 , H01L29/2003 , H01L29/7787
摘要： A semiconductor structure is disclosed that includes a silicon carbide wafer having a diameter of at least 100 mm with a Group III nitride heterostructure on the wafer that exhibits high uniformity in a number of characteristics. These include: a standard deviation in sheet resistivity across the wafer less than three percent; a standard deviation in electron mobility across the wafer of less than 1 percent; a standard deviation in carrier density across the wafer of no more than about 3.3 percent; and a standard deviation in conductivity across the wafer of about 2.5 percent.
摘要翻译：公开了一种半导体结构，其包括具有至少100mm直径的碳化硅晶片，晶片上的III族氮化物异质结构在许多特性上表现出高均匀性。这些包括：晶片上电阻率的标准偏差小于3％; 晶片上电子迁移率的标准偏差小于1％; 晶圆上载流子密度的标准偏差不超过约3.3％; 并且晶片上的电导率的标准偏差约为2.5％。

9. 发明申请

US20060152519A1 Method for operating low power programmable processor 有权
标题翻译：低功耗可编程处理器的运行方法
公开(公告)号：US20060152519A1
公开(公告)日：2006-07-13
申请号：US11374947
申请日：2006-03-13
申请人： Edward Hutchins , Brian Angell , Paul Kim
发明人： Edward Hutchins , Brian Angell , Paul Kim
IPC分类号： G09G5/37
CPC分类号： G06T15/005 , G06F9/3001 , G06F9/30025 , G06T1/20
摘要： A graphics processor is disclosed having a programmable Arithmetic Logic Unit (ALU) stage for processing pixel packets. Scalar arithmetic operations are performed in the ALUs to implement a graphics function.
摘要翻译：公开了具有用于处理像素分组的可编程算术逻辑单元（ALU）级的图形处理器。在ALU中执行标量算术运算以实现图形功能。

10. 发明申请

US20050280655A1 Kill bit graphics processing system and method 有权
标题翻译：杀死位图形处理系统和方法
公开(公告)号：US20050280655A1
公开(公告)日：2005-12-22
申请号：US10846201
申请日：2004-05-14
申请人： Edward Hutchins , Brian Angell
发明人： Edward Hutchins , Brian Angell
IPC分类号： G06T15/00 , G09G5/00
CPC分类号： G06T15/005
摘要： A present invention pixel processing system and method permit complicated three dimensional images to be rendered with shallow graphics pipelines including reduced gate counts and also facilitates power conservation. Pixel packet information includes pixel surface attribute values are retrieved in a single unified data fetch stage. At a data fetch pipestage a determination may be made if the pixel packet information contributes to an image display presentation (e.g., a depth comparison of Z values is performed determine if the pixel is occluded). A pixel packet status indicator (e.g., a kill bit) is set in the sideband portion of a pixel packet and the pixel packet is forwarded for processing in accordance with the pixel packet status indicator. The status indicator is a kill bit is set to prevent logic components from clocking information for a payload portion of the pixel packet if the status indicator indicates the pixel packet payload does not contribute to the image display presentation while continuing to clock pixel packet sideband information.
摘要翻译：本发明的像素处理系统和方法允许使用包括减少的栅极数量的浅图形管线来呈现复杂的三维图像，并且还有助于功率节省。像素分组信息包括像素表面属性值在单个统一数据获取阶段检索。在数据提取管线处，可以确定像素分组信息是否有助于图像显示呈现（例如，执行Z值的深度比较来确定像素是否被遮挡）。像素分组状态指示符（例如，杀死比特）被设置在像素分组的边带部分中，并且像素分组被转发以根据像素分组状态指示符进行处理。如果状态指示符指示像素分组有效载荷对图像显示呈现不起作用，同时继续对像素分组边带信息进行时钟处理，则状态指示符是设置为防止逻辑组件针对像素分组的有效载荷部分的时钟信息。

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