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1. 发明申请

US20130163713A1 METHODS, APPARATUSES, AND CIRCUITS FOR BIMODAL DISABLE CIRCUITS 有权
标题翻译：双向禁用电路的方法，装置和电路
公开(公告)号：US20130163713A1
公开(公告)日：2013-06-27
申请号：US13333850
申请日：2011-12-21
申请人： Eric Booth , Tyler Gomm , Kallol Mazumder , Scott E. Smith , John F. Schreck
发明人： Eric Booth , Tyler Gomm , Kallol Mazumder , Scott E. Smith , John F. Schreck
IPC分类号： G06M11/00 , H03K17/00
CPC分类号： H03L1/00 , G06F1/10 , H03K5/132 , H03K5/133 , H03K21/38
摘要： Circuits, integrated circuits, and methods are disclosed for bimodal disable circuits. In one such example method, a counter is maintained, with the counter indicating a logic level at which an output signal will be disabled during at least a portion of one of a plurality of disable cycles. The logic level indicated by the counter is transitioned. An input signal is provided as the output signal responsive to the enable signal indicating that the output signal is to be enabled, and the output signal is disabled at the logic level indicated by the counter responsive to the enable signal indicating that the output signal is to be disabled.
摘要翻译：公开了用于双模禁止电路的电路，集成电路和方法。在一个这样的示例性方法中，维持计数器，其中计数器指示在多个禁用周期中的至少一个的至少一部分期间输出信号将被禁用的逻辑电平。由计数器指示的逻辑电平转换。响应于指示输出信号被使能的使能信号，输出信号被提供作为输出信号，并且输出信号在由计数器指示的逻辑电平处被禁用，响应于使能信号，指示输出信号为被禁用

2. 发明授权

US08466726B2 Duty cycle correction systems and methods 有权
标题翻译：占空比校正系统和方法
公开(公告)号：US08466726B2
公开(公告)日：2013-06-18
申请号：US13420459
申请日：2012-03-14
申请人： Yasuo Satoh , Eric Booth
发明人： Yasuo Satoh , Eric Booth
IPC分类号： H03K3/017
CPC分类号： H03K5/1565 , H03L7/0805 , H03L7/0812 , H03L7/087
摘要： Duty cycle correction systems and methods of adjusting duty cycles are provided. One such duty cycle correction system includes a duty cycle adjustor and a variable delay line coupled to the duty cycle adjustor. First and second phase detectors have first inputs coupled to the duty cycle adjustor through an inverter and second inputs coupled to the variable delay line. The phase detectors cause the delay line to align rising or falling edges of signals at the output of the delay line with rising or falling edges, respectively, of signals at the output of the inverter. The controller simultaneously causes the duty cycle adjustor to adjust the duty cycle of the output clock signal until the rising and falling edges of signals at the output of the delay line are aligned with rising and falling edges, respectively, of signals at the output of the inverter.
摘要翻译：提供了占空比校正系统和调整占空比的方法。一个这种占空比校正系统包括一个占空比调节器和一个与占空比调节器耦合的可变延迟线。第一和第二相位检测器具有通过反相器耦合到占空比调节器的第一输入端和耦合到可变延迟线的第二输入端。相位检测器使延迟线在延迟线的输出端分别与反相器输出端的信号的上升沿或下降沿对齐信号的上升沿或下降沿。控制器同时使占空比调节器调整输出时钟信号的占空比，直到延迟线输出端的信号的上升沿和下降沿分别与输出端的信号的上升沿和下降沿对齐逆变器。

3. 发明授权

US08143928B2 Duty cycle correction systems and methods 有权
标题翻译：占空比校正系统和方法
公开(公告)号：US08143928B2
公开(公告)日：2012-03-27
申请号：US13098154
申请日：2011-04-29
申请人： Yasuo Satoh , Eric Booth
发明人： Yasuo Satoh , Eric Booth
IPC分类号： H03K3/017
CPC分类号： H03K5/1565 , H03L7/0805 , H03L7/0812 , H03L7/087
摘要： Duty cycle correction systems and methods of adjusting duty cycles are provided. One such duty cycle correction system includes a duty cycle adjustor and a variable delay line coupled to the output of the duty cycle adjustor. First and second phase detectors have first inputs coupled to the output of the duty cycle adjustor through an inverter and second inputs coupled to the output of the variable delay line. The phase detectors cause the delay line to align rising or falling edges of signals at the output of the delay line with rising or falling edges, respectively, of signals at the output of the inverter. The controller simultaneously causes the duty cycle adjustor to adjust the duty cycle of the output clock signal until the rising and falling edges of signals at the output of the delay line are aligned with rising and falling edges, respectively, of signals at the output of the inverter.
摘要翻译：提供了占空比校正系统和调整占空比的方法。一个这样的占空比校正系统包括一个占空比调节器和一个与占空比调节器输出端耦合的可变延迟线。第一和第二相位检测器具有通过反相器耦合到占空比调节器的输出的第一输入端和耦合到可变延迟线的输出的第二输入端。相位检测器使延迟线在延迟线的输出端分别与反相器输出端的信号的上升沿或下降沿对齐信号的上升沿或下降沿。控制器同时使占空比调节器调整输出时钟信号的占空比，直到延迟线输出端的信号的上升沿和下降沿分别与输出端的信号的上升沿和下降沿对齐逆变器。

4. 发明授权

US07928782B2 Digital locked loops and methods with configurable operating parameters 有权
标题翻译：数字锁定环路和具有可配置工作参数的方法
公开(公告)号：US07928782B2
公开(公告)日：2011-04-19
申请号：US12361320
申请日：2009-01-28
申请人： Eric Booth , George G. Carey , Brian Callaway
发明人： Eric Booth , George G. Carey , Brian Callaway
IPC分类号： H03L7/06
CPC分类号： H03L7/0814 , H03L7/091
摘要： A locked loop may have an adjustable hysteresis and/or a tracking speed that can be programmed by a user of an electronic device containing the locked loop or controlled by an integrated circuit device containing the locked loop during operation of the device. The looked loop may include a phase detector having a variable hysteresis, which may be coupled to receive a reference clock signal and an output clock signal from a phase adjustment circuit through respective frequency dividers that can vary the rate at which the phase detector compares the phase of the output clock signal to the phase of the reference clock signal, thus varying the tracking speed of the loop. The hysteresis and tracking speed of the locked loop may be programmed using a variety of means, such as by a temperature sensor for the electronic device, a mode register, a memory device command decoder, etc.
摘要翻译：锁定环路可以具有可调整的滞后和/或跟踪速度，该速度可以由包含锁定环路的电子设备的用户编程，或者由设备操作期间由包含锁定环路的集成电路设备控制。锁定环路可以包括具有可变滞后的相位检测器，其可以被耦合以通过相应的分频器从相位调整电路接收参考时钟信号和输出时钟信号，该分频器可以改变相位检测器比较相位的输出时钟信号到参考时钟信号的相位，从而改变回路的跟踪速度。锁定环路的滞后和跟踪速度可以使用各种手段进行编程，例如通过电子设备的温度传感器，模式寄存器，存储设备命令解码器等。

5. 发明申请

US20090116602A1 High speed, wide frequency-range, digital phase mixer and methods of operation 有权
标题翻译：高速，宽频范围，数字相位混频器及操作方法
公开(公告)号：US20090116602A1
公开(公告)日：2009-05-07
申请号：US11983201
申请日：2007-11-07
申请人： Chang-Ki Kwon , Eric Booth
发明人： Chang-Ki Kwon , Eric Booth
IPC分类号： H04L7/00
CPC分类号： H03L7/00 , G06G7/12 , H03K17/00 , H03L7/0814
摘要： The present disclosure is directed to a unit phase mixer in combination with an input buffer. The unit phase mixer has a pull-up path for pulling an output terminal up to a first voltage. The pull-up path has a first transistor responsive to a first enable signal and a series connected second transistor responsive to a first clock signal. The unit phase mixer has a pull-down path for pulling the output terminal down to a second voltage. The pull-down path has a third transistor responsive to a second clock signal and a series connected fourth transistor responsive to a second enable signal. The input buffer skews the first and second clock signals by different amounts to enable a break-before-make method of operation so that the first voltage is not connected to the second voltage. The unit phase mixer can be used as a building block in more complex mixers which may include the ability to weight the input clocks as well as providing feed-forward paths for certain of the signals. Because of the rules governing abstract, this abstract should not be used to construe the claims.
摘要翻译：本公开涉及与输入缓冲器组合的单位相混合器。单相混合器具有用于将输出端拉至第一电压的上拉路径。所述上拉路径具有响应于第一使能信号的第一晶体管和响应于第一时钟信号的串联连接的第二晶体管。单相混合器具有用于将输出端子向下拉到第二电压的下拉路径。所述下拉路径具有响应于第二时钟信号的第三晶体管和响应于第二使能信号的串联连接的第四晶体管。输入缓冲器使第一和第二时钟信号偏移不同的量，以使得能够进行先前的断开操作方法，使得第一电压不连接到第二电压。单相混频器可以用作更复杂的混频器中的构建块，其可以包括对输入时钟加权的能力以及为某些信号提供前馈路径。由于抽象的规则，本摘要不应用于解释索赔。

6. 发明申请

US20070062411A1 Fluorescent security ink using carbon nanotubes 有权
标题翻译：使用碳纳米管的荧光防伪墨水
公开(公告)号：US20070062411A1
公开(公告)日：2007-03-22
申请号：US10572720
申请日：2004-09-02
申请人： R. Weisman , Sergei Bachilo , Eric Booth
发明人： R. Weisman , Sergei Bachilo , Eric Booth
IPC分类号： C09D11/00 , C09K11/06 , H01F1/00
CPC分类号： B82Y25/00 , B82Y30/00 , C09D11/50 , C09K11/02 , C09K11/65 , H01F1/0045 , Y10T428/24835 , Y10T428/25
摘要： The present invention is directed toward fluorescent inks and markers comprising carbon nanotubes. The present invention is also directed toward methods of making such inks and markers and to methods of using such inks and markers, especially for security applications (e.g., anti-counterfeiting). Such inks and markers rely on the unique fluorescent properties of semiconducting carbon nanotubes.
摘要翻译：本发明涉及包含碳纳米管的荧光油墨和标记物。本发明还涉及制备这种油墨和标记物的方法以及使用这种油墨和标记物的方法，特别是用于安全应用（例如防伪）。这种油墨和标记依赖于半导体碳纳米管的独特荧光特性。

7. 发明授权

US08437726B2 High speed, wide frequency-range, digital phase mixer and methods of operation 有权
公开(公告)号：US08437726B2
公开(公告)日：2013-05-07
申请号：US13041118
申请日：2011-03-04
申请人： Chang-Ki Kwon , Eric Booth
发明人： Chang-Ki Kwon , Eric Booth
IPC分类号： H04B1/26
CPC分类号： H03L7/00 , G06G7/12 , H03K17/00 , H03L7/0814
摘要： The present disclosure is directed to a unit phase mixer in combination with an input buffer. The unit phase mixer has a pull-up path for pulling an output terminal up to a first voltage. The pull-up path has a first transistor responsive to a first enable signal and a series connected second transistor responsive to a first clock signal. The unit phase mixer has a pull-down path for pulling the output terminal down to a second voltage. The pull-down path has a third transistor responsive to a second clock signal and a series connected fourth transistor responsive to a second enable signal. The input buffer skews the first and second clock signals by different amounts to enable a break-before-make method of operation so that the first voltage is not connected to the second voltage. The unit phase mixer can be used as a building block in more complex mixers which may include the ability to weight the input clocks as well as providing feed-forward paths for certain of the signals. Because of the rules governing abstract, this abstract should not be used to construe the claims.

8. 发明申请

US20110175655A1 DIGITAL LOCKED LOOPS AND METHODS WITH CONFIGURABLE OPERATING PARAMETERS 有权
标题翻译：数字锁定机身和方法与可配置的操作参数
公开(公告)号：US20110175655A1
公开(公告)日：2011-07-21
申请号：US13074785
申请日：2011-03-29
申请人： Eric Booth , George G. Carey , Brian Callaway
发明人： Eric Booth , George G. Carey , Brian Callaway
IPC分类号： H03L7/06
CPC分类号： H03L7/0814 , H03L7/091
摘要： A locked loop may have an adjustable hysteresis and/or a tracking speed that can be programmed by a user of an electronic device containing the locked loop or controlled by an integrated circuit device containing the locked loop during operation of the device. The looked loop may include a phase detector having a variable hysteresis, which may be coupled to receive a reference clock signal and an output clock signal from a phase adjustment circuit through respective frequency dividers that can vary the rate at which the phase detector compares the phase of the output clock signal to the phase of the reference clock signal, thus varying the tracking speed of the loop. The hysteresis and tracking speed of the locked loop may be programmed using a variety of means, such as by a temperature sensor for the electronic device, a mode register, a memory device command decoder, etc.
摘要翻译：锁定环路可以具有可调整的滞后和/或跟踪速度，该速度可以由包含锁定环路的电子设备的用户编程，或者由设备操作期间由包含锁定环路的集成电路设备控制。锁定环路可以包括具有可变滞后的相位检测器，其可以被耦合以通过相应的分频器从相位调整电路接收参考时钟信号和输出时钟信号，该分频器可以改变相位检测器比较相位的输出时钟信号到参考时钟信号的相位，从而改变回路的跟踪速度。锁定环路的滞后和跟踪速度可以使用各种手段进行编程，例如通过电子设备的温度传感器，模式寄存器，存储设备命令解码器等。

9. 发明申请

US20110156788A1 HIGH SPEED, WIDE FREQUENCY-RANGE, DIGITAL PHASE MIXER AND METHODS OF OPERATION 有权
标题翻译：高速，宽频范围，数字相位混频器及操作方法
公开(公告)号：US20110156788A1
公开(公告)日：2011-06-30
申请号：US13041118
申请日：2011-03-04
申请人： Chang-Ki Kwon , Eric Booth
发明人： Chang-Ki Kwon , Eric Booth
IPC分类号： H03H11/16
CPC分类号： H03L7/00 , G06G7/12 , H03K17/00 , H03L7/0814
摘要： The present disclosure is directed to a unit phase mixer in combination with an input buffer. The unit phase mixer has a pull-up path for pulling an output terminal up to a first voltage. The pull-up path has a first transistor responsive to a first enable signal and a series connected second transistor responsive to a first clock signal. The unit phase mixer has a pull-down path for pulling the output terminal down to a second voltage. The pull-down path has a third transistor responsive to a second clock signal and a series connected fourth transistor responsive to a second enable signal. The input buffer skews the first and second clock signals by different amounts to enable a break-before-make method of operation so that the first voltage is not connected to the second voltage. The unit phase mixer can be used as a building block in more complex mixers which may include the ability to weight the input clocks as well as providing feed-forward paths for certain of the signals. Because of the rules governing abstract, this abstract should not be used to construe the claims.
摘要翻译：本公开涉及与输入缓冲器组合的单位相混合器。单相混合器具有用于将输出端拉至第一电压的上拉路径。所述上拉路径具有响应于第一使能信号的第一晶体管和响应于第一时钟信号的串联连接的第二晶体管。单相混合器具有用于将输出端子向下拉到第二电压的下拉路径。所述下拉路径具有响应于第二时钟信号的第三晶体管和响应于第二使能信号的串联连接的第四晶体管。输入缓冲器使第一和第二时钟信号偏移不同的量，以使得能够进行先前的断开操作方法，使得第一电压不连接到第二电压。单相混频器可以用作更复杂的混频器中的构建块，其可以包括对输入时钟加权的能力以及为某些信号提供前馈路径。由于抽象的规则，本摘要不应用于解释索赔。

10. 发明授权

US07940103B2 Duty cycle correction systems and methods 有权
标题翻译：占空比校正系统和方法
公开(公告)号：US07940103B2
公开(公告)日：2011-05-10
申请号：US12400495
申请日：2009-03-09
申请人： Yasuo Satoh , Eric Booth
发明人： Yasuo Satoh , Eric Booth
IPC分类号： H03K3/017
CPC分类号： H03K5/1565 , H03L7/0805 , H03L7/0812 , H03L7/087
摘要： Duty cycle correction systems and methods of adjusting duty cycles are provided. One such duty cycle correction system includes a duty cycle adjustor and a variable delay line coupled to the output of the duty cycle adjustor. First and second phase detectors have first inputs coupled to the output of the duty cycle adjustor through an inverter and second inputs coupled to the output of the variable delay line. The phase detectors cause the delay line to align rising or falling edges of signals at the output of the delay line with rising or falling edges, respectively, of signals at the output of the inverter. The controller simultaneously causes the duty cycle adjustor to adjust the duty cycle of the output clock signal until the rising and falling edges of signals at the output of the delay line are aligned with rising and falling edges, respectively, of signals at the output of the inverter.
摘要翻译：提供了占空比校正系统和调整占空比的方法。一个这样的占空比校正系统包括一个占空比调节器和一个与占空比调节器输出端耦合的可变延迟线。第一和第二相位检测器具有通过反相器耦合到占空比调节器的输出的第一输入端和耦合到可变延迟线的输出的第二输入端。相位检测器使延迟线在延迟线的输出端分别与反相器输出端的信号的上升沿或下降沿对齐信号的上升沿或下降沿。控制器同时使占空比调节器调整输出时钟信号的占空比，直到延迟线输出端的信号的上升沿和下降沿分别与输出端的信号的上升沿和下降沿对齐逆变器。

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