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1. 发明授权

US6018370A Current source and threshold voltage generation method and apparatus for HHK video circuit 失效
公开(公告)号：US6018370A
公开(公告)日：2000-01-25
申请号：US848387
申请日：1997-05-08
申请人： Mehrdad Nayebi , Duc Ngo
发明人： Mehrdad Nayebi , Duc Ngo
IPC分类号： G05F1/56 , H04N5/08 , H04N5/10
CPC分类号： H04N5/08 , G05F1/56
摘要： A current source and threshold voltage generation circuit generates a current, through a ratio of devices, and a corresponding threshold voltage signal, to be utilized by a timing circuit for generating a timing ramp and determining when the timing ramp crosses the threshold voltage signal. The current is generated through a current generation circuit, using a ratio of matched devices. Preferably, the matched devices are transistors. The current is then utilized by a timing circuit to charge a charge storage device to a level above the level of the threshold voltage signal. The current is also mirrored, appropriately increased and used to generate the threshold voltage signal which is compared to the charge stored on the charge storage device. Accordingly, any errors in the generation of the current are also reflected in the level of the threshold voltage signal, thereby eliminating the potential for errors in the timing ramp signal generated by the timing circuit. Preferably, the charge storage device is a capacitor and the timing circuit is an HHK video circuit. The preferred embodiment of the current source and threshold voltage generation circuit is implemented within an integrated circuit and does not require any external components.

2. 发明授权

US5774185A Method of and apparatus for removing equalizing pulses without using external pins 失效
标题翻译：不使用外部引脚去除均衡脉冲的方法和装置
公开(公告)号：US5774185A
公开(公告)日：1998-06-30
申请号：US583972
申请日：1996-01-11
申请人： Mehrdad Nayebi , Duc Ngo , Chun Yee
发明人： Mehrdad Nayebi , Duc Ngo , Chun Yee
IPC分类号： H04N5/08 , H04N5/10
CPC分类号： H04N5/08
摘要： A circuit for removing every other equalizing pulse from a signal representing the sync pulses of a composite video signal, generates an output signal representative of every horizontal synchronization pulse and every other vertical synchronization pulse within the composite video signal. A sync separator circuit separates the synchronization pulses from the composite video signal. An output of the sync separator circuit includes all of the horizontal synchronization pulses and vertical synchronization pulses. The vertical synchronization pulses include equalizing pulses and serration pulses which have a frequency which is twice the frequency of the horizontal synchronization pulses. A capacitor is used to store charge. A current source charges the capacitor. A transistor controlled by the output signal provides a discharge path for the capacitor. A comparator monitors the voltage level stored across the capacitor and enables an output generation circuit when the level of charge stored across the capacitor is above a predetermined threshold level. The value of the capacitor and the value of the current source cause the time required to raise the voltage level across the capacitor to a level above the predetermined threshold level to be less than the time between horizontal synchronization pulses and greater than the time between vertical synchronization pulses. The output generation circuit generates the output signal as a pulse signal representative of the synchronization pulse. The output generation circuit is only enabled when the voltage level across the capacitor is greater than the predetermined threshold level. Therefore, the pulse signal is generated for every horizontal synchronization pulse and for every other vertical synchronization pulse.
摘要翻译：用于从表示复合视频信号的同步脉冲的信号中去除每隔一个均衡脉冲的电路产生表示复合视频信号内的每个水平同步脉冲和每隔一个垂直同步脉冲的输出信号。同步分离器电路将同步脉冲与复合视频信号分离。同步分离器电路的输出包括所有水平同步脉冲和垂直同步脉冲。垂直同步脉冲包括具有水平同步脉冲频率的两倍的频率的均衡脉冲和锯齿脉冲。电容用于存储电荷。电流源为电容充电。由输出信号控制的晶体管提供电容器的放电路径。比较器监视存储在电容器两端的电压电平，并且当存储在电容器两端的电荷电平高于预定阈值电平时使能输出产生电路。电容器的值和电流源的值导致将电容器两端的电压电平提高到高于预定阈值水平所需的时间，以便小于水平同步脉冲之间的时间并且大于垂直同步之间的时间脉冲。输出产生电路产生作为表示同步脉冲的脉冲信号的输出信号。仅当电容器两端的电压电平大于预定阈值电平时，才能使能输出产生电路。因此，对于每个水平同步脉冲和每隔一个垂直同步脉冲产生脉冲信号。

3. 发明授权

US5121015A Voltage controlled delay element 失效
标题翻译：电压控制延时元件
公开(公告)号：US5121015A
公开(公告)日：1992-06-09
申请号：US613178
申请日：1990-11-14
申请人： Duc Ngo
发明人： Duc Ngo
IPC分类号： H03K4/94 , H03K5/00 , H03K5/13
CPC分类号： H03K4/94 , H03K5/133 , H03K2005/00104 , H03K2005/00189
摘要： A BICMOS voltage controllable delay element has an input terminal that is supplied with an input voltage from a pair of BICMOS transmission gates. The input voltage is either a control voltage or a reference voltage as determined by the state of an input signal. A first BICMOS inverter is switched by the input voltage and the charge and discharge of a timing capacitor is controlled by the magnitude of the control voltage and the reference voltage. A second BICMOS inverter responds to the timing capacitor voltage for developing an output signal voltage that is phase delayed with respect to the input signal voltage. A precision delay element using a PLL circuit is shown as are a frequency multiplier arrangement and a pulse width measuring arrangement.
摘要翻译： BICMOS电压可控延迟元件具有从一对BICMOS传输门提供输入电压的输入端。输入电压是由输入信号的状态确定的控制电压或参考电压。第一个BICMOS逆变器由输入电压切换，定时电容器的充放电由控制电压和参考电压的大小控制。第二个BICMOS逆变器响应于定时电容器电压，用于开发相对于输入信号电压相位延迟的输出信号电压。示出了使用PLL电路的精密延迟元件是倍频器布置和脉冲宽度测量装置。

4. 发明授权

US6046776A Burst gate pulse generator 失效
标题翻译：突发脉冲发生器
公开(公告)号：US6046776A
公开(公告)日：2000-04-04
申请号：US110091
申请日：1998-07-02
申请人： Duc Ngo , Chun Yee
发明人： Duc Ngo , Chun Yee
IPC分类号： H04N9/455 , H04N9/44 , H04N9/445
CPC分类号： H04N9/455
摘要： A burst gate pulse generator generates a burst gate signal representative of a time period during which a burst signal is present within an input composite video signal. Each period of the input composite video signal includes a horizontal synchronization pulse, a burst signal and a video information signal. The burst gate pulse generator detects the end of the horizontal synchronization signal and begins the burst pulse at the end of the horizontal synchronization signal. A timing circuit including a charge storage device and a charge delivery device controls the duration of the burst pulse. When the burst pulse is activated the charge delivery device begins building a charge across the charge storage device until a threshold value is reached. Once the charge stored across the charge storage device equals the threshold value the burst pulse is deactivated. During the time when the burst pulse is active, the burst signal will be present on the input composite video signal. In order to have a fixed value for a sync tip of the horizontal synchronization pulse and to be able to apply certain thresholds within the burst gate pulse generator, the sync tip of the input composite video signal is clamped to a level equal to 2.5 volts. Preferably, the burst pulse has a duration equal to 3.5 nanoseconds.
摘要翻译：突发门脉冲发生器产生表示脉冲信号存在于输入复合视频信号内的时间周期的突发门控信号。输入复合视频信号的每个周期包括水平同步脉冲，突发信号和视频信息信号。脉冲串脉冲发生器检测水平同步信号的结束，并在水平同步信号结束时开始脉冲串脉冲。包括电荷存储装置和电荷输送装置的定时电路控制脉冲串脉冲的持续时间。当突发脉冲被激活时，电荷传送装置开始在电荷存储装置之间建立电荷，直到达到阈值。一旦存储在电荷存储装置中的电荷等于阈值，脉冲串脉冲被去激活。在突发脉冲有效时，突发信号将存在于输入复合视频信号上。为了具有用于水平同步脉冲的同步尖端的固定值，并且能够在突发门脉冲发生器内施加某些阈值，将输入复合视频信号的同步尖端钳位到等于2.5伏的电平。优选地，突发脉冲具有等于3.5纳秒的持续时间。

5. 发明授权

US5844621A Burst gate pulse generator 失效
公开(公告)号：US5844621A
公开(公告)日：1998-12-01
申请号：US583986
申请日：1996-01-11
申请人： Duc Ngo , Chun Yee
发明人： Duc Ngo , Chun Yee
IPC分类号： H04N9/455
CPC分类号： H04N9/455
摘要： A burst gate pulse generator generates a burst gate signal representative of a time period during which a burst signal is present within an input composite video signal. Each period of the input composite video signal includes a horizontal synchronization pulse, a burst signal and a video information signal. The burst gate pulse generator detects the end of the horizontal synchronization signal and begins the burst pulse at the end of the horizontal synchronization signal. A timing circuit including a charge storage device and a charge delivery device controls the duration of the burst pulse. When the burst pulse is activated the charge delivery device begins building a charge across the charge storage device until a threshold value is reached. Once the charge stored across the charge storage device equals the threshold value the burst pulse is deactivated. During the time when the burst pulse is active, the burst signal will be present on the input composite video signal. In order to have a fixed value for a sync tip of the horizontal synchronization pulse and to be able to apply certain thresholds within the burst gate pulse generator, the sync tip of the input composite video signal is clamped to a level equal to 2.5 volts. Preferably, the burst pulse has a duration equal to 3.5 nanoseconds.

6. 发明授权

US5828254A Error regulator circuit for sample and hold phase locked loops 失效
标题翻译：用于采样和保持锁相环的误差调节器电路
公开(公告)号：US5828254A
公开(公告)日：1998-10-27
申请号：US584925
申请日：1996-01-11
申请人： Mehrdad Nayebi , Duc Ngo
发明人： Mehrdad Nayebi , Duc Ngo
IPC分类号： H03L7/089 , H03L7/14 , H03L7/06
CPC分类号： H03L7/0895 , H03L7/14
摘要： An error regulator circuit for use within a charge pump circuit of a phase-locked loop monitors levels of the control signals used to control the charge pump circuit. When one of the control signals remains at a predetermined voltage level for a predetermined period of time, indicating that the charge pump circuit is in a hold mode or an inactive period of time, the current sources within the charge pump used to charge and discharge a charge pump capacitor are temporarily disabled. During a hold or inactive period when one of the control signals used to control the charge pump circuit remains at the predetermined voltage level for more than a predetermined period of time, the current sources of the charge pump circuit are disabled and the charge pump circuit is prevented from charging or discharging the charge pump capacitor until the current sources are re-enabled, thereby allowing the charge pump circuit to maintain an appropriate level of charge across the capacitor during an inactive or hold period. The current sources are re-enabled when the control signal which was at the predetermined voltage level for more than the predetermined period of time is no longer at the predetermined voltage level.
摘要翻译：在锁相环的电荷泵电路内使用的误差调节器电路监视用于控制电荷泵电路的控制信号的电平。当一个控制信号在预定时间段内保持在预定电压电平时，指示电荷泵电路处于保持模式或无效时间段，用于对电荷泵充电和放电的电荷源电荷泵电容器暂时禁用。在用于控制电荷泵电路的控制信号中的一个控制信号保持在预定电压电压超过预定时间段的保持或不活动期间，电荷泵电路的电流源被禁用，电荷泵电路为防止电荷泵电容器充电或放电直到电流源被重新使能，从而允许电荷泵电路在非活动或保持期间在电容器两端保持适当的电荷水平。当处于预定电压电平超过预定时间段的控制信号不再处于预定电压电平时，电流源被重新启用。

7. 发明授权

US5247229A Adaptive scan control having horizontal scan locked clock system 失效
标题翻译：具有水平扫描锁定时钟系统的自适应扫描控制
公开(公告)号：US5247229A
公开(公告)日：1993-09-21
申请号：US822476
申请日：1992-01-17
申请人： Duc Ngo , Kishan R. Pulluru , Gopal K. Srivastava
发明人： Duc Ngo , Kishan R. Pulluru , Gopal K. Srivastava
IPC分类号： H03L7/081 , H04N5/12
CPC分类号： H04N5/126 , H03L7/081
摘要： A television receiver includes conventional systems for receiving a broadcast type signal and displaying the received signal upon a cathode ray tube. Vertical and horizontal scan system oscillators and controls produce vertical and horizontal scan signal synchronized to the reference sync signals. A scan clock system cooperates with the horizontal oscillator and control system to produce horizontal scan related signals which are synchronized to the CRT scan.
摘要翻译：电视接收机包括用于接收广播型信号并在阴极射线管上显示接收信号的常规系统。垂直和水平扫描系统振荡器和控制器产生与参考同步信号同步的垂直和水平扫描信号。扫描时钟系统与水平振荡器和控制系统配合产生与CRT扫描同步的水平扫描相关信号。

8. 发明授权

US5926063A Method of and apparatus for selectively engaging an internal trap filter and implementing an external trap filter through a single pin 失效
标题翻译：用于选择性地接合内部陷阱滤波器并通过单个引脚实现外部陷波滤波器的方法和装置
公开(公告)号：US5926063A
公开(公告)日：1999-07-20
申请号：US852919
申请日：1997-05-08
申请人： Mehrdad Nayebi , Duc Ngo
发明人： Mehrdad Nayebi , Duc Ngo
IPC分类号： H04N9/78 , H03K5/00 , H03H11/04
CPC分类号： H04N9/78
摘要： A method of and apparatus for selectively engaging an internal trap filter and implementing an external trap filter through a single pin routes a separate luminance signal through the pin or through an internal trap filter based on the logical voltage level at the pin. When implementing an external trap filter the external components comprising the filter are coupled between the pin and ground and a voltage level of the pin is maintained at a logical low voltage level. When the pin is at a logical low voltage level, two path switches are closed and the separate luminance signal is routed through the pin to be filtered by the external trap filter. The internal trap filter is engaged by coupling a precision resistor between the pin and a power supply voltage thereby pulling the voltage level of the pin to a logical high voltage level and opening the two path switches to bypass the pin and route the separate luminance signal through an internal trap filter. When the voltage level of the pin is at a logical high voltage level, a bias switch is closed thereby providing a bias current, created from the voltage drop across the precision resistor, to the internal trap filter. The internal trap filter is activated by the bias current and filters the separate luminance signal according to the value of the bias current, before the separate luminance signal is combined with the separate chrominance signal. The value of the bias current is controlled by the value of the precision resistor.
摘要翻译：用于选择性地接合内部陷波滤波器并且通过单个引脚实现外部陷波滤波器的方法和装置基于引脚处的逻辑电压电平来引导通过引脚或通过内部陷波滤波器的单独的亮度信号。当实现外部陷波滤波器时，包括滤波器的外部组件耦合在引脚和地之间，并且引脚的电压电平保持在逻辑低电压电平。当引脚处于逻辑低电压电平时，两个通道开关闭合，并且单独的亮度信号通过引脚布线，以通过外部陷波滤波器进行滤波。内部陷波滤波器通过在引脚和电源电压之间耦合精密电阻而被接合，从而将引脚的电压电平拉至逻辑高电压电平，并打开两个路径开关绕过引脚并将分离的亮度信号通过内部陷阱过滤器。当引脚的电压电平处于逻辑高电压电平时，偏置开关闭合，从而提供从精密电阻两端产生的电压降到内部陷波滤波器的偏置电流。内部陷波滤波器由偏置电流激活，并且在单独的亮度信号与分离的色度信号组合之前，根据偏置电流的值对单独的亮度信号进行滤波。偏置电流的值由精密电阻的值控制。

9. 发明授权

US5105108A Delay circuit with phase locked loop control 失效
标题翻译：延迟电路采用锁相环控制
公开(公告)号：US5105108A
公开(公告)日：1992-04-14
申请号：US614188
申请日：1990-11-14
申请人： Duc Ngo
发明人： Duc Ngo
IPC分类号： H03K5/00 , H03K5/13 , H03L7/081 , H03L7/16 , H04N9/893
CPC分类号： H03L7/0805 , H03K5/133 , H03L7/0812 , H03L7/16 , H04N9/893 , H03K2005/00104 , H03K2005/00189
摘要： A delay circuit includes an output voltage controllable BICMOS delay element that is coupled to a phase locked loop that develops a control voltage. The control voltage is applied to the output BICMOS delay element and to another BICMOS delay element in the phase locked loop. An input voltage is applied to the phase locked loop and, along with the output of the phase locked loop, to the output BICMOS delay element.
摘要翻译：延迟电路包括耦合到产生控制电压的锁相环的输出电压可控BICMOS延迟元件。控制电压被施加到输出BICMOS延迟元件和锁相环中的另一个BICMOS延迟元件。输入电压施加到锁相环，并与锁相环路的输出一起施加到输出BICMOS延迟元件。

10. 发明授权

US6141064A Luminance signal generation circuit with single clamp in closed loop configuration 失效
标题翻译：亮度信号发生电路采用单夹钳闭环配置
公开(公告)号：US6141064A
公开(公告)日：2000-10-31
申请号：US848385
申请日：1997-05-08
申请人： Mehrdad Nayebi , Duc Ngo
发明人： Mehrdad Nayebi , Duc Ngo
IPC分类号： H04N9/72
CPC分类号： H04N9/72
摘要： A luminance signal generation circuit with single clamp generates a separate luminance signal Y by combining RGB input signals in a weighted manner within a Y-Matrix circuit. During a burst period the single clamping circuit is enabled. When enabled, the single clamping circuit compares the separate luminance signal Y to a constant reference voltage signal. A difference signal, representing the difference between the separate luminance signal Y and the constant reference voltage signal, is used to adjust a blanking level of the RGB input signals until the blanking level of the separate luminance signal Y is equal to the constant reference voltage signal. During the non-burst periods the single clamping circuit is disabled and the Y-Matrix circuit combines the RGB input signals into the separate luminance signal Y. Preferably, the single clamping circuit sets the blank level of the separate luminance signal Y to a level equal to two volts. NPN transistor follower circuits are utilized within the clamping circuit and with input receiving circuits to provide the RGB input signals to the Y-Matrix circuit.
摘要翻译：具有单个钳位的亮度信号产生电路通过在Y-Matrix电路内以加权的方式组合RGB输入信号来产生单独的亮度信号Y. 在脉冲串期间，单个钳位电路被使能。当使能时，单个钳位电路将分离的亮度信号Y与恒定的参考电压信号进行比较。使用表示分立亮度信号Y与恒定基准电压信号之间的差的差分信号来调整RGB输入信号的消隐电平，直到分离亮度信号Y的消隐电平等于恒定参考电压信号。在非突发时段期间，单个钳位电路被禁用，并且Y矩阵电路将RGB输入信号组合成单独的亮度信号Y.优选地，单个钳位电路将分离的亮度信号Y的空白电平设置为等于到两伏。在钳位电路内使用NPN晶体管跟随器电路，并且输入接收电路将RGB输入信号提供给Y-Matrix电路。

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