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1. 发明授权

US5899714A Fabrication of semiconductor structure having two levels of buried regions 失效
标题翻译：具有两层埋藏区域的半导体结构的制造
公开(公告)号：US5899714A
公开(公告)日：1999-05-04
申请号：US471061
申请日：1995-06-06
申请人： Douglas R. Farrenkopf , Richard B. Merrill , Samar Saha , Kevin E. Brehmer , Kamesh Gadepally , Philip J. Cacharelis
发明人： Douglas R. Farrenkopf , Richard B. Merrill , Samar Saha , Kevin E. Brehmer , Kamesh Gadepally , Philip J. Cacharelis
IPC分类号： H01L21/761 , H01L21/822 , H01L21/8249 , H01L27/02 , H01L27/06 , H01L27/088 , H01L27/14
CPC分类号： H01L21/761 , H01L21/822 , H01L21/8249 , H01L27/0623 , H01L27/088 , H01L27/0203 , Y10S148/085
摘要： Integrated circuits suitable for high-performance applications, especially mixed signal products that have analog and digital sections, are fabricated from a semiconductor structure in which lower buried regions of opposite conductivity types are situated along a lower semiconductor interface between a semiconductive substrate and an overlying lower semiconductive layer. An upper buried region of a selected conductivity type is situated along an upper semiconductor interface between the lower semiconductive layer and an overlying upper semiconductive layer. Another upper buried region of opposite conductivity type to the first-mentioned upper buried region is preferably situated along the upper semiconductor interface. The upper semiconductive layer contains P-type and N-type device regions in which transistor zones are situated. The semiconductor structure is configured so that at least one of each of the P-type and N-type device regions is electrically isolated from the substrate. Complementary bipolar transistors can be integrated with complementary field-effect transistors in the structure.
摘要翻译：适用于高性能应用的集成电路，特别是具有模拟和数字部分的混合信号产品由半导体结构制造，其中相反导电类型的较低掩埋区域沿着半导体衬底和上覆下层之间的下半导体界面半导体层。所选择的导电类型的上掩埋区域沿着下半导体层和上半导电层之间的上半导体界面设置。优选地，与上述上部掩埋区域相反的导电类型的另一个上部掩埋区域沿着上半导体界面设置。上半导体层包含晶体管区所在的P型和N型器件区。半导体结构被配置为使得每个P型和N型器件区中的至少一个与衬底电隔离。互补双极晶体管可以与结构中的互补场效应晶体管集成。

2. 发明授权

US5889315A Semiconductor structure having two levels of buried regions 失效
标题翻译：具有两层埋藏区域的半导体结构
公开(公告)号：US5889315A
公开(公告)日：1999-03-30
申请号：US393622
申请日：1995-02-23
申请人： Douglas R. Farrenkopf , Richard B. Merrill , Samar Saha , Kevin E. Brehmer , Kamesh Gadepally , Philip J. Cacharelis
发明人： Douglas R. Farrenkopf , Richard B. Merrill , Samar Saha , Kevin E. Brehmer , Kamesh Gadepally , Philip J. Cacharelis
IPC分类号： H01L21/761 , H01L21/822 , H01L21/8249 , H01L27/02 , H01L27/06 , H01L27/088 , H01L29/00
CPC分类号： H01L21/761 , H01L21/822 , H01L21/8249 , H01L27/0623 , H01L27/088 , H01L27/0203 , Y10S148/085
摘要： Integrated circuits suitable for high-performance applications, especially mixed signal products that have analog and digital sections, are fabricatable from a semiconductor structure having two levels of buried regions. In a typical embodiment lower buried regions of opposite conductivity types are situated along a lower semiconductor interface between a semiconductive substrate and an overlying lower semiconductive layer. Upper buried regions of opposite conductivity type are similarly situated along an upper semiconductor interface between the lower semiconductive layer and an overlying upper semiconductive layer. The upper semiconductive layer contains P-type and N-type device regions in which transistor zones are situated. The semiconductor structure is normally configured so that at least one of each of the P-type and N-type device regions is electrically isolated from the substrate. Complementary bipolar transistors can be integrated with complementary field-effect transistors in the structure.
摘要翻译：适合于高性能应用的集成电路，特别是具有模拟和数字部分的混合信号产品，可从具有两级埋入区域的半导体结构制造。在典型的实施例中，相反导电类型的较低掩埋区域沿着半导体衬底和上覆下半导体层之间的下半导体界面设置。相反导电类型的上掩埋区类似地位于下半导体层和上半导电层之间的上半导体界面处。上半导体层包含晶体管区所在的P型和N型器件区。半导体结构通常被配置为使得每个P型和N型器件区域中的至少一个与衬底电隔离。互补双极晶体管可以与结构中的互补场效应晶体管集成。

3. 发明授权

US5854099A DMOS process module applicable to an E.sup.2 CMOS core process 失效
标题翻译： DMOS工艺模块适用于E2 CMOS核心工艺
公开(公告)号：US5854099A
公开(公告)日：1998-12-29
申请号：US870920
申请日：1997-06-06
申请人： Douglas R. Farrenkopf
发明人： Douglas R. Farrenkopf
IPC分类号： H01L21/8238 , H01L21/8239 , H01L21/8247
CPC分类号： H01L29/7809 , H01L21/8238 , H01L27/1052 , H01L29/66719 , H01L29/086
摘要： In a method of fabricating a DMOS transistor structure, wherein the DMOS transistor structure includes an active semiconductor substrate region having a tub of N-type conductivity formed therein, the N-type tub being formed over an N.sup.+ buried region, and having an N.sup.+ sinker region formed therein at an edge of the N-type tub, the N.sup.+ sinker region extending from a surface of the N-type tub to the N.sup.+ buried region, a pad oxide layer is formed on the N-tub and on the N.sup.+ sinker region. A composite mask is then formed on the silicon nitride layer, and includes etched openings such that the surface of the periphery of the N-type tub is exposed and the interface between the N-type tub and the N.sup.+ sinker region is exposed. The composite mask is then utilized to form field oxide isolation regions in the semiconductor substrate region at the periphery of the N-type tub and at the interface between the N-type tub and the N.sup.+ sinker region. After removing the composite mask, a P-body mask is formed on the nitride layer. Finally, a metal layer is formed over the structure resulting from the above-defined steps to form metal contacts to the P-body region, the gate contact and the N.sup.+ sinker region.
摘要翻译：在制造DMOS晶体管结构的方法中，其中DMOS晶体管结构包括其中形成有N型导电槽的有源半导体衬底区域，N型阱形成在N +掩埋区上，并具有N +沉降片形成在N型槽的边缘的N +沉降片区域，N +沉降片区域从N型槽的表面延伸到N +掩埋区域，在N形槽和N +沉降片区域上形成衬垫氧化物层。然后在氮化硅层上形成复合掩模，并且包括蚀刻开口，使得N型槽的周边的表面露出，并且露出N型槽和N +沉降片区域之间的界面。然后利用复合掩模在N型槽周边的半导体衬底区域和N型槽和N +沉降片区域之间的界面处形成场氧化物隔离区。在去除复合掩模之后，在氮化物层上形成P体掩模。最后，在由上述步骤形成的结构上形成金属层，以形成与P体区域，栅极接触和N +沉降片区域的金属接触。

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