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1. 发明授权

US4771377A Microcode control apparatus 失效
标题翻译：微码控制装置
公开(公告)号：US4771377A
公开(公告)日：1988-09-13
申请号：US798522
申请日：1985-11-15
申请人： Donald C. Wiser , David I. Epstein , Mark D. Hummel , Patrick J. Weiler , Thomas J. Myer
发明人： Donald C. Wiser , David I. Epstein , Mark D. Hummel , Patrick J. Weiler , Thomas J. Myer
IPC分类号： G06F9/22 , G06F9/30
CPC分类号： G06F9/223
摘要： Apparatus and method is disclosed for controlling the timing of the addressing, fetching and executing of microinstructions in a data processing system such that delayed sequencing microinstructions, stretched delayed sequencing microinstructions and immediate sequencing microinstructions may be intermixed in the microinstruction stream. Circuitry is provided to determine the type of sequencing specified for each microinstruction and control the generation of the execution cycle signal and the microinstruction address clocking signal such that these signals occur in the appropriate time sequence to accomplish the specified sequencing.
摘要翻译：公开了用于控制数据处理系统中寻址，取出和执行微指令的定时的装置和方法，使得延迟测序微指令，延迟测序微指令和立即测序微指令可以混合在微指令流中。提供电路以确定为每个微指令指定的排序类型，并控制执行周期信号和微指令地址时钟信号的产生，使得这些信号以合适的时间顺序出现以完成指定的顺序。

2. 发明授权

US4901235A Data processing system having unique multilevel microcode architecture 失效
标题翻译：数据处理系统具有独特的多级微代码架构
公开(公告)号：US4901235A
公开(公告)日：1990-02-13
申请号：US546572
申请日：1983-10-28
申请人： Chandra R. Vora , Donald C. Wiser , Mark B. Hecker , Robert N. Murdoch
发明人： Chandra R. Vora , Donald C. Wiser , Mark B. Hecker , Robert N. Murdoch
IPC分类号： G06F9/22 , G06F9/28 , G06F9/38
CPC分类号： G06F9/223 , G06F9/28 , G06F9/3885
摘要： A data processing system which includes a central processor unit which has an arithmetic logic unit (ALU) for performing fixed point arithmetic operations and a separate floating point unit (FPU) for performing floating point operations and which uses multi-level microcode architecture wherein each unit has its own control store (a "horizontal" store) which responds to addresses of execution control signals supplied thereto from a common control store (a "vertical" store) to produce horizontal microinstructions for performing ALU and FPU operations, respectively. Selected ones of such addresses are recognized for ALU operations by the CPU control store only, other selected ones are recognized for FPU operations by the FPU control store only, while still other selected ones are recognized for both ALU and FPU operations by both control stores so that such operations can be performed simultaneously in parallel.
摘要翻译：一种数据处理系统，其包括具有用于执行定点算术运算的算术逻辑单元（ALU）和用于执行浮点运算的单独浮点单元（FPU）的中央处理器单元，并且使用多级微代码架构，其中每个单元具有其自己的控制存储器（“水平”存储器），其响应于从公共控制存储器（“垂直”存储器）提供的执行控制信号的地址，以分别产生用于执行ALU和FPU操作的水平微指令。所选择的这些地址仅由CPU控制存储器识别用于ALU操作，仅由FPU控制存储器识别用于FPU操作的其他选择的操作，同时由两个控制存储器为ALU和FPU操作识别其他选定的一个。这样的操作可以并行同时执行。

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