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    • 5. 发明授权
    • Analog switch with a low flatness operating characteristic
    • 具有低平整度工作特性的模拟开关
    • US08054122B2
    • 2011-11-08
    • US12633777
    • 2009-12-08
    • Dianbo Guo
    • Dianbo Guo
    • H03L5/00
    • H03K17/145H03K2217/0018H03K2217/0036H03K2217/0054
    • An analog switch includes a transistor whose source connected to a signal input and whose drain is connected to a signal output. An output of a gate control circuit is connected to the transistor gate. A first input of the gate control circuit is connected to the source of the transistor. The gate control circuit responds to a logic transition of an enable signal received at a second input by pre-charging a substantially constant gate-to-source voltage across the transistor. This voltage is stored by a gate-to-source connected capacitor. In one steady-state logic condition of the enable signal, the gate control circuit operates to turn off the transistor. In another steady-state logic condition of the enable signal, the gate control circuit permits the signal received at the signal input to drive the gate of the transistor with a voltage offset by the substantially constant gate-to-source voltage stored on the capacitor.
    • 模拟开关包括其源极连接到信号输入并且其漏极连接到信号输出的晶体管。 栅极控制电路的输出端连接到晶体管栅极。 栅极控制电路的第一输入端连接到晶体管的源极。 栅极控制电路通过对晶体管两端的基本恒定的栅极 - 源极电压进行预充电来响应在第二输入端接收的使能信号的逻辑转换。 该电压由栅极到源极连接的电容器存储。 在使能信号的一个稳态逻辑条件下,栅极控制电路用于关断晶体管。 在使能信号的另一个稳态逻辑条件下,门控制电路允许在信号输入处接收到的信号以由存储在电容器上的基本上恒定的栅极 - 源极电压的电压偏移来驱动晶体管的栅极。
    • 8. 发明申请
    • ON-CHIP MEASUREMENT OF CAPACITANCE FOR MICRO-ELECTRO-MECHANICAL SYSTEM (MEMS) ACTUATOR CIRCUIT
    • 微电子机械系统(MEMS)执行器电路的电容芯片测量
    • US20120153973A1
    • 2012-06-21
    • US12972596
    • 2010-12-20
    • Dianbo Guo
    • Dianbo Guo
    • G01R27/26
    • B81C99/003G01R27/2605
    • A micro-electro-mechanical system (MEMS) actuator circuit and method. The circuit includes a current mirror, a voltage divider having an interior contact and coupled between the mirror output and a potential, an operational amplifier having an input coupled to the interior contact and a switch having input/output contacts separately coupled to the amplifier output and the mirror input and having a switch control. The amplifier output can be coupled to a digital control circuit which can be coupled to the switch control contact and to a digital to analog circuit (DAC) which can be coupled to the digital control circuit and to another amplifier input. An enable signal at the switch control couples the switch input/output contacts together. The capacitance of a MEMS capacitor coupled to the mirror output is determined by measurement of time for the amplifier output to switch from one level to another following a change in DAC output potential.
    • 微机电系统(MEMS)致动器电路及方法。 电路包括电流镜,具有内部接触并耦合在镜面输出和电位之间的分压器,具有耦合到内部触点的输入的运算放大器和具有分别耦合到放大器输出的输入/输出触点的开关,以及 镜像输入并具有开关控制。 放大器输出可以耦合到数字控制电路,数字控制电路可耦合到开关控制触点和耦合到数字控制电路和另一个放大器输入的数模电路(DAC)。 开关控制器处的使能信号将开关输入/输出触点耦合在一起。 耦合到镜像输出的MEMS电容器的电容由DAC输出电位变化后,通过测量放大器输出从一个电平切换到另一个电平的时间来确定。
    • 10. 发明授权
    • Negative analog switch design
    • 负模拟开关设计
    • US07924085B2
    • 2011-04-12
    • US12488287
    • 2009-06-19
    • Dianbo Guo
    • Dianbo Guo
    • H03K3/01
    • H03K17/6874H03K17/162H03K2217/0018
    • A transmission gate includes first and second MOS transistors of opposite conductivity type coupled in parallel with each other. Each transistor includes a body connection that is separately biased by corresponding first and second biasing circuits. The first biasing circuit generates a first bias voltage having a voltage level that is generated as a function of the signal at the first node and a first (for example, positive) reference voltage. The second biasing circuit generates a second bias voltage having a voltage level that is generated as a function of the signal at the first node and a second (for examples ground) reference voltage.
    • 传输门包括彼此并联耦合的相反导电类型的第一和第二MOS晶体管。 每个晶体管包括由相应的第一和第二偏置电路单独偏置的主体连接。 第一偏置电路产生具有作为第一节点处的信号和第一(例如,正)参考电压的函数产生的电压电平的第一偏置电压。 第二偏置电路产生具有作为第一节点处的信号和第二(例如,接地)参考电压的函数产生的电压电平的第二偏置电压。