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1. 发明申请

US20050160215A1 Flow through asynchronous elastic FIFO apparatus and method for implementing multi-engine parsing and authentication 审中-公开
标题翻译：流过异步弹性FIFO装置和实现多引擎解析和认证的方法
公开(公告)号：US20050160215A1
公开(公告)日：2005-07-21
申请号：US10760446
申请日：2004-01-20
申请人： Daniel Moertl , Dennis Reetz , Donald Ziebarth
发明人： Daniel Moertl , Dennis Reetz , Donald Ziebarth
IPC分类号： G06F5/14 , G11C5/00
CPC分类号： G06F5/14 , G06F2205/102
摘要： A flow through asynchronous elastic first-in, first-out (FIFO) apparatus and method are provided for implementing multi-engine parsing and authentication. A FIFO random access memory (RAM) has a data input for receiving data and control information and a data output for outputting the data and control information. The FIFO RAM includes a plurality of locations for storing a plurality of words, each word including a set number of bits. Write clocked logic is provided for loading the data and control information to the FIFO RAM at a first clock frequency. Asynchronous read clocked logic is provided for outputting the data and control information from the FIFO RAM at a second clock frequency. The first clock frequency of the write clocked logic and the second clock frequency of the asynchronous read clocked logic and a data width of the FIFO RAM are selectively provided for outputting the data and control information from the FIFO RAM with no back pressure.
摘要翻译：提供了通过异步弹性先进先出（FIFO）装置和方法的流程，用于实现多引擎解析和认证。 FIFO随机存取存储器（RAM）具有用于接收数据和控制信息的数据输入和用于输出数据和控制信息的数据输出。 FIFO RAM包括用于存储多个单词的多个位置，每个单词包括设定位数。提供写时钟逻辑用于以第一时钟频率将数据和控制信息加载到FIFO RAM。提供异步读时钟逻辑，用于以第二时钟频率从FIFO RAM输出数据和控制信息。选择性地提供写时钟逻辑的第一时钟频率和异步读时钟逻辑的第二时钟频率以及FIFO RAM的数据宽度，用于从没有背压的FIFO RAM输出数据和控制信息。

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