会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 1. 发明授权
    • Microprocessor having a prefetch cache
    • 具有预取缓存的微处理器
    • US06317810B1
    • 2001-11-13
    • US08882691
    • 1997-06-25
    • Herbert Lopez-AguadoDenise ChiacchiaWilliam L. LynchGary Lauterbach
    • Herbert Lopez-AguadoDenise ChiacchiaWilliam L. LynchGary Lauterbach
    • G06F1208
    • G06F9/3802G06F9/3455G06F9/383G06F9/3832G06F9/3861G06F12/0862G06F2212/6022G06F2212/6028
    • A central processing unit of a computer includes a single-ported data cache and a dual-ported prefetch cache. The data cache accommodates a first pipeline and the prefetch cache, which is much smaller than the data cache, accommodates both the first pipeline and a second pipeline. If a data cache miss occurs, a row of data corresponding to the specified address is stored in the data cache and the prefetch cache. Thereafter, if a prefetch cache hit occurs, a row of data corresponding to a prefetch address is loaded into the prefetch cache. The prefetch address may, for instance, be generated by adding a fixed increment to the specified address. This operation frequently results in the prefetch cache storing data soon requested by a computer program. When this condition is achieved, the data corresponding to the subsequent address request is rapidly retrieved from cache memory without incurring memory latencies associated with the external cache, the primary memory, and the secondary memory. In this manner, the prefetch cache of the present invention facilitates improved memory latencies. Further, the prefetch cache allows for two data requests to be processed simultaneously without a corresponding two-fold increase in cost of data cache memory.
    • 计算机的中央处理单元包括单端口数据高速缓存和双端口预取缓存。 数据高速缓存容纳第一流水线,并且比数据高速缓存小得多的预取缓存容纳第一流水线和第二流水线。 如果发生数据高速缓存未命中,则与指定地址对应的数据行存储在数据高速缓存和预取缓存中。 此后,如果发生预取缓存命中,则将与预取地址对应的数据行加载到预取高速缓存中。 预取地址可以例如通过向指定的地址添加固定的增量来生成。 此操作经常导致预取缓存存储计算机程序很快请求的数据。 当达到这种条件时,与高速缓冲存储器快速地检索对应于后续地址请求的数据,而不会引起与外部高速缓存,主存储器和辅助存储器相关联的存储器延迟。 以这种方式,本发明的预取高速缓存有利于改进的存储器延迟。 此外,预取缓存允许同时处理两个数据请求,而数据高速缓冲存储器的成本增加相应的两倍。
    • 2. 发明授权
    • Apparatus and method for generating a stride used to derive a prefetch
address
    • 用于产生用于导出预取地址的步幅的装置和方法
    • US6098154A
    • 2000-08-01
    • US881050
    • 1997-06-25
    • Herbert Lopez-AguadoDenise ChiacchiaGary Lauterbach
    • Herbert Lopez-AguadoDenise ChiacchiaGary Lauterbach
    • G06F12/08G06F12/00
    • G06F12/0897
    • A central processing unit (CPU) of a computer has a data caching unit which includes a novel dual-ported prefetch cache configured in parallel with a conventional single-ported data cache. In response to a data cache miss, the requested data is fetched from external memory and loaded into the data cache and into the prefetch cache. Thereafter, if a prefetch cache hit occurs, the physical address of the corresponding data request is provided to a prefetch engine which, in turn, adds a stride to the physical address to derive a prefetch address. This prefetch address identifies data which is predicted to be soon requested in subsequent instructions of the computer program. Data corresponding to the prefetch address is then retrieved from external memory and loaded into the prefetch cache. This prefetching operation frequently results in the prefetch cache storing data that is requested by subsequently executed instructions in a computer program. When this condition occurs, data is immediately retrieved from the prefetch cache and provided to execution units within the CPU, thereby eliminating latencies associated with external memory.
    • 计算机的中央处理单元(CPU)具有数据高速缓存单元,其包括与常规单端口数据高速缓存并行配置的新型双端口预取高速缓存。 响应于数据高速缓存未命中,请求的数据从外部存储器获取并加载到数据高速缓存并进入预取缓存。 此后,如果发生预取缓存命中,则相应数据请求的物理地址被提供给预取引擎,预取引擎又向物理地址添加步幅以导出预取地址。 该预取地址标识预计将在计算机程序的后继指令中即将要求的数据。 然后从外部存储器检索与预取地址对应的数据,并加载到预取缓存中。 这种预取操作经常导致预取高速缓存存储由计算机程序中的随后执行的指令请求的数据。 当发生这种情况时,立即从预取高速缓存中检索数据,并提供给CPU中的执行单元,从而消除与外部存储器相关的延迟。
    • 3. 发明授权
    • Apparatus and method for generating a stride used to derive a prefetch
address
    • 用于产生用于导出预取地址的步幅的装置和方法
    • US6138212A
    • 2000-10-24
    • US882517
    • 1997-06-25
    • Denise ChiacchiaHerbert Lopez-AguadoGary Lauterbach
    • Denise ChiacchiaHerbert Lopez-AguadoGary Lauterbach
    • G06F9/38G06F12/08
    • G06F9/383G06F12/0862G06F9/3455G06F9/3832G06F2212/6022G06F2212/6024G06F2212/6026
    • A central processing unit (CPU) of a computer has a data caching unit which includes a novel dual-ported prefetch cache configured in parallel with a conventional single-ported data cache. If a data cache miss occurs, the requested data is loaded into the data cache and into the prefetch cache. Thereafter, each data request which results in a prefetch cache hit triggers the prefetching of data into the prefetch cache. A data load history tracking circuit maintains a running history of instructions that request data from external memory, and uses the resulting loop heuristics of these instructions to generate a stride. The stride is used to derive a prefetch address which identifies data that is predicted to be soon requested in subsequent instructions. Data corresponding to the prefetch address is then loaded into the prefetch cache. Thus, where a subsequent instruction requests data which has been prefetched into the prefetch cache, latencies associated with external memory may be hidden, thereby increasing the data bandwidth of the CPU.
    • 计算机的中央处理单元(CPU)具有数据高速缓存单元,其包括与常规单端口数据高速缓存并行配置的新型双端口预取高速缓存。 如果发生数据高速缓存未命中,则将请求的数据加载到数据高速缓存中并进入预取缓存。 此后,导致预取高速缓存命中的每个数据请求触发将数据预取到预取高速缓存中。 数据负载历史跟踪电路维护从外部存储器请求数据的指令的运行历史,并且使用这些指令的结果循环启发式来产生步幅。 步幅用于导出预取地址,其识别在随后的指令中预测即将要求的数据。 与预取地址相对应的数据然后被加载到预取缓存中。 因此,在后续指令请求已经预取的数据到预取高速缓存中的情况下,与外部存储器相关联的延迟可能被隐藏,从而增加了CPU的数据带宽。
    • 4. 发明授权
    • Method for invalidating data identified by software compiler
    • 使软件编译器识别的数据无效的方法
    • US5996061A
    • 1999-11-30
    • US881044
    • 1997-06-25
    • Herbert Lopez-AguadoDenise ChiacchiaGary Lauterbach
    • Herbert Lopez-AguadoDenise ChiacchiaGary Lauterbach
    • G06F9/38G06F12/08G06F9/00
    • G06F9/383G06F12/0848G06F12/0862G06F9/3455G06F9/3832G06F2212/6022G06F2212/6028
    • A central processing unit (CPU) of a computer includes a novel prefetch cache configured in parallel with a conventional data cache. If a data cache miss occurs, the requested data is fetched from external memory and loaded into the data cache and into the prefetch cache. Thereafter, if a prefetch cache hit occurs, a prefetch address is derived, and data corresponding to the prefetch address is prefetched into the prefetch cache. This prefetching operation frequently results in the prefetch cache storing data that is requested by subsequently executed instructions in a computer program, thereby eliminating latencies associated with external memory. A software compiler of the computer ensures the validity of data stored in the prefetch cache. The software compiler alerts the prefetch cache that data stored within the prefetch cache is to be rewritten and, in response thereto, the prefetch cache invalidates the data. In this manner, data may be invalidated without requiring use of conventional cache snooping mechanisms, thereby increasing the speed with which data in cache memory may be invalidated. The ability to more quickly invalidate data in cache memory allows data previously considered "non-cachable" to be stored, and remain valid, in cache memory.
    • 计算机的中央处理单元(CPU)包括与常规数据高速缓存并行配置的新型预取缓存。 如果发生数据高速缓存未命中,则从外部存储器中获取所请求的数据,并将其加载到数据高速缓存中并进入预取缓存。 此后,如果发生预取高速缓存命中,则导出预取地址,并且将预取地址对应的数据预取到预取高速缓存中。 该预取操作经常导致预取高速缓存存储由计算机程序中的随后执行的指令请求的数据,从而消除与外部存储器相关联的延迟。 计算机的软件编译器确保存储在预取缓存中的数据的有效性。 软件编译器警告预取缓存,存储在预取高速缓存中的数据将被重写,并且响应于此,预取高速缓存使数据无效。 以这种方式,数据可能无效,而不需要使用常规的高速缓存侦听机制,从而增加高速缓冲存储器中的数据可能无效的速度。 能够更快速地使高速缓存中的数据无效使得先前认为“不可高速”的数据在高速缓冲存储器中被存储并保持有效。