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1. 发明授权

US4589067A Full floating point vector processor with dynamically configurable multifunction pipelined ALU 失效
标题翻译：具有可动态配置的多功能流水线ALU的全浮点矢量处理器
公开(公告)号：US4589067A
公开(公告)日：1986-05-13
申请号：US498877
申请日：1983-05-27
申请人： John B. Porter , David W. Altmann , Bruno A. Mattedi , Ralph Jones
发明人： John B. Porter , David W. Altmann , Bruno A. Mattedi , Ralph Jones
IPC分类号： G06F17/16 , G06F9/22 , G06F9/38 , G06F15/16 , G06F7/38 , G06F7/49
CPC分类号： G06F9/3887 , G06F9/226 , G06F9/30036 , G06F9/3879
摘要： A full floating point vector processor includes a master processing unit having DMA I/O means, a wide bandwidth data memory having static RAM and/or interleaved dynamic RAM, an address generator operative to provide address generation for data loaded in the data memory, a concurrently operating pipeline control sequencer operative to provide fully programmable horizontal format microinstructions synchronously with the addresses generated by the address generator, and a pipelined arithmetic and logical unit responsive to the addressed data and to the synchronously provided microinstructions and operative to evaluate one of a user selectable plurality of computationally intensive functions. The address generator, the pipeline controlsequencer, and the master processing unit are configured in parallel. The address generator includes means operative to provide pipeline input and output data dependent address generation. The microinstruction controlled pipelined arithmetic and logical unit includes two register files controllably interconnectable over feedforward and feedback data flow paths, a user selectable fixed or floating point format multiplier, a user selectable fixed or floating point format arithmetic and logical unit, and a sign latch coupled between the arithmetic and logical unit and one of the register files. The sign latch microinstruction control is operative to provide the arithmetic and logical unit with a data dependent decison making capability. A microinstruction controlled write address FIFO and a read address FIFO are coupled to the data memory.
摘要翻译：完整的浮点矢量处理器包括具有DMA I / O装置的主处理单元，具有静态RAM和/或交错动态RAM的宽带数据存储器，地址发生器，用于为数据存储器中加载的数据提供地址生成，同时操作的管线控制定序器，其可操作地与由地址发生器产生的地址同步地提供完全可编程的水平格式微指令;以及流水线运算和逻辑单元，其响应于所寻址的数据和同步提供的微指令，并可操作以评估用户可选择的一个多个计算密集型功能。地址发生器，管线控制顺序器和主处理单元并行配置。地址发生器包括用于提供流水线输入和输出数据相关地址生成的装置。微指令控制的流水线算术和逻辑单元包括两个寄存器文件，其可通过前馈和反馈数据流路径可控地互连，用户可选择的固定或浮点格式乘法器，用户可选择的固定或浮点格式算术和逻辑单元，以及符号锁存器算术和逻辑单元之间的一个寄存器文件。符号锁存微指令控制可操作以向算术和逻辑单元提供依赖于数据的分解能力。微指令控制写地址FIFO和读地址FIFO耦合到数据存储器。

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