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1. 发明申请

US20130270572A1 GROUP III-N HFET WITH A GRADED BARRIER LAYER 有权
标题翻译：具有分级障碍层的III-N组HFET
公开(公告)号：US20130270572A1
公开(公告)日：2013-10-17
申请号：US13448348
申请日：2012-04-16
申请人： David F. Brown , Miroslav Micovic
发明人： David F. Brown , Miroslav Micovic
IPC分类号： H01L29/205 , H01L21/22 , H01L21/20
CPC分类号： H01L29/205 , H01L29/2003 , H01L29/201 , H01L29/42316 , H01L29/66431 , H01L29/66462 , H01L29/7783
摘要： A device and a method of making said wherein the device wherein the device has a group III-nitride buffer deposited on a substrate; and a group III-nitride heterostructure disposed on a surface of the group III-nitride buffer, wherein the group III-nitride heterostructure has a group III-nitride channel and a group III-nitride barrier layer disposed on a surface of the group III-nitride channel, the group III-nitride barrier layer including Al as one of its constituent group III elements, the Al having a mole fraction which varies at least throughout a portion of said group III-nitride barrier layer.
摘要翻译：一种制造所述装置和方法，其中所述装置其中所述装置具有沉积在基板上的III族氮化物缓冲层; 和III族氮化物异质结构，其中所述III族氮化物异质结构具有III族氮化物沟道和III族氮化物阻挡层，所述III族氮化物阻挡层设置在所述III族氮化物缓冲层的表面上，氮化物沟道，III族氮化物阻挡层包括Al作为其组成III族元素之一，Al具有至少在所述III族氮化物阻挡层的一部分上变化的摩尔分数。

2. 发明申请

US20080237811A1 METHOD FOR PRESERVING PROCESSING HISTORY ON A WAFER 审中-公开
标题翻译：保存加工历史的方法
公开(公告)号：US20080237811A1
公开(公告)日：2008-10-02
申请号：US11694057
申请日：2007-03-30
申请人： Rohit Pal , David F. Brown
发明人： Rohit Pal , David F. Brown
IPC分类号： H01L23/544
CPC分类号： H01L22/20
摘要： A method for capturing process history includes performing at least a first process for forming features on a semiconducting substrate. A first cap is formed over a first region of the semiconducting substrate after performing the first process. At least a second process is performed for forming the features in a second region other than the first region while leaving the first cap in place to thereby prevent the features in the first region covered by the first cap from being exposed to the second process. A first characteristic of a first feature is measured in the first region, and a second characteristic of a second feature in the second region is measured. A wafer includes a first partially completed feature disposed in a first region. A first cap is formed above the first partially completed feature. A second partially completed feature is disposed in a second region of the wafer different than the first region. The second partially completed feature is at a later stage of completion than the first partially completed feature.
摘要翻译：用于捕获工艺历史的方法包括至少执行用于在半导体衬底上形成特征的第一工艺。在执行第一处理之后，在半导体基板的第一区域上形成第一盖。执行至少第二过程，用于在除了第一区域之外的第二区域中形成特征，同时将第一盖留在适当位置，从而防止第一盖子覆盖的第一区域中的特征暴露于第二过程。在第一区域中测量第一特征的第一特征，并且测量第二区域中的第二特征的第二特征。晶片包括设置在第一区域中的第一部分完成特征。在第一部分完成的特征之上形成第一盖。第二部分完成的特征被布置在不同于第一区域的晶片的第二区域中。第二部分完成的功能处于完成的后期，而不是第一部分完成的功能。

3. 发明申请

US20150056764A1 Methods relating to a Group III HFET with a Graded Barrier Layer 有权
标题翻译：涉及具有梯度屏障层的III类HFET的方法
公开(公告)号：US20150056764A1
公开(公告)日：2015-02-26
申请号：US14479223
申请日：2014-09-05
申请人： David F. Brown , Miroslav Micovic
发明人： David F. Brown , Miroslav Micovic
IPC分类号： H01L29/205 , H01L29/20 , H01L29/66
CPC分类号： H01L29/205 , H01L29/2003 , H01L29/201 , H01L29/42316 , H01L29/66431 , H01L29/66462 , H01L29/7783
摘要： A device and a method of making said wherein the device wherein the device has a group III-nitride buffer deposited on a substrate; and a group III-nitride heterostructure disposed on a surface of the group III-nitride buffer, wherein the group III-nitride heterostructure has a group III-nitride channel and a group III-nitride barrier layer disposed on a surface of the group III-nitride channel, the group III-nitride barrier layer including Al as one of its constituent group III elements, the Al having a mole fraction which varies at least throughout a portion of said group III-nitride barrier layer.
摘要翻译：一种制造所述装置和方法，其中所述装置其中所述装置具有沉积在基板上的III族氮化物缓冲层; 和III族氮化物异质结构，其中所述III族氮化物异质结构具有III族氮化物沟道和III族氮化物阻挡层，所述III族氮化物阻挡层设置在所述III族氮化物缓冲层的表面上，氮化物沟道，III族氮化物阻挡层包括Al作为其组成III族元素之一，Al具有至少在所述III族氮化物阻挡层的一部分上变化的摩尔分数。

4. 发明授权

US08860091B2 Group III-N HFET with a graded barrier layer 有权
标题翻译：具有梯度阻挡层的III-N族HFET
公开(公告)号：US08860091B2
公开(公告)日：2014-10-14
申请号：US13448348
申请日：2012-04-16
申请人： David F. Brown , Miroslav Micovic
发明人： David F. Brown , Miroslav Micovic
IPC分类号： H01L31/072
CPC分类号： H01L29/205 , H01L29/2003 , H01L29/201 , H01L29/42316 , H01L29/66431 , H01L29/66462 , H01L29/7783
摘要： A device and a method of making said wherein the device wherein the device has a group III-nitride buffer deposited on a substrate; and a group III-nitride heterostructure disposed on a surface of the group III-nitride buffer, wherein the group III-nitride heterostructure has a group III-nitride channel and a group III-nitride barrier layer disposed on a surface of the group III-nitride channel, the group III-nitride barrier layer including Al as one of its constituent group III elements, the Al having a mole fraction which varies at least throughout a portion of said group III-nitride barrier layer.
摘要翻译：一种制造所述装置和方法，其中所述装置其中所述装置具有沉积在基板上的III族氮化物缓冲层; 和III族氮化物异质结构，其中所述III族氮化物异质结构具有III族氮化物沟道和III族氮化物阻挡层，所述III族氮化物阻挡层设置在所述III族氮化物缓冲层的表面上，氮化物沟道，III族氮化物阻挡层包括Al作为其组成III族元素之一，Al具有至少在所述III族氮化物阻挡层的一部分上变化的摩尔分数。

5. 发明授权

US08853709B2 III-nitride metal insulator semiconductor field effect transistor 有权
标题翻译： III族氮化物金属绝缘子半导体场效应晶体管
公开(公告)号：US08853709B2
公开(公告)日：2014-10-07
申请号：US13456039
申请日：2012-04-25
申请人： Rongming Chu , David F. Brown , Xu Chen , Adam J. Williams , Karim S. Boutros
发明人： Rongming Chu , David F. Brown , Xu Chen , Adam J. Williams , Karim S. Boutros
IPC分类号： H01L29/778 , H01L29/20
CPC分类号： H01L29/66462 , H01L29/2003 , H01L29/2006 , H01L29/205 , H01L29/4236 , H01L29/513 , H01L29/66522 , H01L29/7786 , H01L29/7787 , H01L29/78
摘要： A field effect transistor (FET) includes a III-Nitride channel layer, a III-Nitride barrier layer on the channel layer, wherein the barrier layer has an energy bandgap greater than the channel layer, a source electrode electrically coupled to one of the III-Nitride layers, a drain electrode electrically coupled to one of the III-Nitride layers, a gate insulator layer stack for electrically insulating a gate electrode from the barrier layer and the channel layer, the gate insulator layer stack including an insulator layer, such as SiN, and an AlN layer, the gate electrode in a region between the source electrode and the drain electrode and in contact with the insulator layer, and wherein the AlN layer is in contact with one of the III-Nitride layers.
摘要翻译：场效应晶体管（FET）包括III-氮化物沟道层，沟道层上的III-氮化物阻挡层，其中该阻挡层具有比该沟道层大的能带隙，该电极与III 氮化物层，电耦合到III族氮化物层之一的漏电极，用于将栅极电极与阻挡层电绝缘的栅极绝缘体层堆叠和沟道层，栅极绝缘体层堆叠包括绝缘体层，例如 SiN和AlN层，栅电极在源电极和漏电极之间的区域中并与绝缘体层接触，并且其中AlN层与III-氮化物层之一接触。

6. 发明授权

US3947027A High performance golf tee 失效
标题翻译：高性能高尔夫球
公开(公告)号：US3947027A
公开(公告)日：1976-03-30
申请号：US469084
申请日：1974-05-13
申请人： David F. Brown
发明人： David F. Brown
IPC分类号： A63B57/00
CPC分类号： A63B57/10
摘要： A high performance golf tee comprises a stem, a cup-shaped ball receptacle on the top of the stem, and a projection extending outwardly from the ball receptacle a sufficient distance such that when a golf ball is placed on the tee and a golf club is swung at the ball, the golf club contacts the projection and imparts motion to the ball before the golf club makes direct contact with the surface of the golf ball. The contact between the golf club and the projection imparts an initial backspin on the ball, and this improves the flight characteristics of the ball. The golf tee may be integrally molded as a unit including the projection or the projection may be formed as an attachment for a conventional golf tee.

7. 发明申请

US20130026495A1 III-Nitride Metal Insulator Semiconductor Field effect Transistor 有权
标题翻译： III-Nitride金属绝缘子半导体场效应晶体管
公开(公告)号：US20130026495A1
公开(公告)日：2013-01-31
申请号：US13456039
申请日：2012-04-25
申请人： Rongming Chu , David F. Brown , Xu Chen , Adam J. Williams , Karim S. Boutros
发明人： Rongming Chu , David F. Brown , Xu Chen , Adam J. Williams , Karim S. Boutros
IPC分类号： H01L29/778 , H01L21/336 , H01L29/205
CPC分类号： H01L29/66462 , H01L29/2003 , H01L29/2006 , H01L29/205 , H01L29/4236 , H01L29/513 , H01L29/66522 , H01L29/7786 , H01L29/7787 , H01L29/78
摘要： A field effect transistor (FET) includes a III-Nitride channel layer, a III-Nitride barrier layer on the channel layer, wherein the barrier layer has an energy bandgap greater than the channel layer, a source electrode electrically coupled to one of the III-Nitride layers, a drain electrode electrically coupled to one of the III-Nitride layers, a gate insulator layer stack for electrically insulating a gate electrode from the barrier layer and the channel layer, the gate insulator layer stack including an insulator layer, such as SiN, and an AlN layer, the gate electrode in a region between the source electrode and the drain electrode and in contact with the insulator layer, and wherein the AlN layer is in contact with one of the III-Nitride layers.
摘要翻译：场效应晶体管（FET）包括III-氮化物沟道层，沟道层上的III-氮化物阻挡层，其中该阻挡层具有比该沟道层大的能带隙，该电极与III 氮化物层，电耦合到III族氮化物层之一的漏电极，用于将栅极电极与阻挡层电绝缘的栅极绝缘体层堆叠和沟道层，栅极绝缘体层堆叠包括绝缘体层，例如 SiN和AlN层，栅极电极在源电极和漏电极之间的区域中并与绝缘体层接触，并且其中AlN层与III-氮化物层之一接触。

8. 发明授权

US6130920A Method and apparatus for accurate synchronization using symbol decision feedback 失效
标题翻译：使用符号决策反馈进行精确同步的方法和装置
公开(公告)号：US6130920A
公开(公告)日：2000-10-10
申请号：US76992
申请日：1998-05-13
申请人： Clinton C. Powell, II , Chun-Ye Chang , David L. Brown , David F. Brown , Robert Karl Schweickert
发明人： Clinton C. Powell, II , Chun-Ye Chang , David L. Brown , David F. Brown , Robert Karl Schweickert
IPC分类号： H03M13/39 , H03M13/23 , H04L7/00 , H04L7/02 , H04L7/04 , H04L25/38 , H04L27/06 , H04L27/14
CPC分类号： H04L7/0062 , H04L7/042
摘要： A circuit (12) for symbol decision directed feedback synchronization includes a current synchonization clock (45) that provides an initial sampling point and selects a detector corresponding to a current symbol decision. The circuit further includes a plurality of detectors (31, 32, 33, and 34) including the detector corresponding to the current symbol decision, a buffer (736) for storing the output of the detector corresponding to the current symbol decision and a processor (300) for seeking within a predetermined window about the initial sampling point for an optimum phase value to provide an adjustment signal which is used by the processor to adjust a subsequent symbol's sychronization clock to provide an optimal sampling point.
摘要翻译：用于符号决定定向反馈同步的电路（12）包括提供初始采样点并选择对应于当前符号判定的检测器的当前同步时钟（45）。电路还包括多个包括与当前符号决定相对应的检测器的检测器（31,32,33和34），用于存储与当前符号判定相对应的检测器的输出的缓冲器（736） 300），用于在关于初始采样点的预定窗口内寻找最佳相位值，以提供由处理器用于调整后续符号的同步时钟以提供最佳采样点的调整信号。

9. 发明授权

US4381458A Back-up electrical power supplies 失效
标题翻译：备用电源
公开(公告)号：US4381458A
公开(公告)日：1983-04-26
申请号：US290104
申请日：1981-08-04
申请人： Michael J. Anstey , David F. Brown
发明人： Michael J. Anstey , David F. Brown
IPC分类号： G06F1/26 , G06F1/30 , G11C5/14 , H01L23/58 , H02J9/06 , H02J9/02
CPC分类号： G11C5/141 , G06F1/26 , G06F1/30 , H01L23/58 , H02J9/06 , H01L2924/0002 , Y10T307/615 , Y10T307/625
摘要： A back-up electrical power supply module provides a back-up supply for a plug-in volatile electrical device such as a memory module. The memory module has a dual-in-line pins which engage socket openings of a standard dual-in-line circuit board connector. The back-up supply module is mounted on top of the memory module and has dual-in-line pins which contact corresponding ones of the pins of the memory module and corresponding socket openings. In this way the back-up supply module and the memory module can be unplugged as a unit and when unplugged, the back-up supply will maintain the contents of the volatile memory module intact.
摘要翻译：备用电源模块为诸如存储器模块的插入式易失性电气设备提供备用电源。存储器模块具有与标准双列直插电路板连接器的插座开口接合的双列直插销。备用电源模块安装在存储器模块的顶部，并具有与内存模块的相应引脚相应的双列直插式引脚和相应的插座开口。以这种方式，备用电源模块和存储模块可以作为一个单元拔下电源，当拔下电源时，备用电源将保持易失性存储器模块的内容不变。

10. 发明授权

US4823233A Circuit assembly 失效
标题翻译：电路组装
公开(公告)号：US4823233A
公开(公告)日：1989-04-18
申请号：US686310
申请日：1984-12-24
申请人： David F. Brown , Michael J. Anstey
发明人： David F. Brown , Michael J. Anstey
IPC分类号： H05K1/14 , H05K7/02 , H05K7/20
CPC分类号： H05K7/023 , H05K1/144 , H05K7/20 , H01L2224/48227 , H01L2224/49171 , H01L2924/1627 , H01L2924/3011
摘要： A circuit assembly includes a mounting structure 10 having walls 11-13, 20 with conductor strips 19 running along the length of the structure. Plate members 14 carrying components such as integrated circuits 16 have conductive areas 18 which contact the conductor strips 19 when the members are inserted into the structure 10. The walls may include slots 15 into which the plate members 14 are slidably engaged. The support structure 10 thus provides physical support for the members 14 as well as electrical interconnection therebetween. Cooling arrangements for the assembly can include apertures 21 in the walls, and/or finning 22.
摘要翻译：电路组件包括具有壁11-13,20的安装结构10，导体条19沿着结构的长度延伸。承载诸如集成电路16的组件的板构件14具有导电区域18，当构件被插入到结构10中时，导电区域18接触导体条19.壁可以包括槽15，板构件14可滑动地接合到槽15中。因此，支撑结构10为构件14提供物理支撑以及它们之间的电互连。组件的冷却装置可以包括壁中的孔21和/或翅片22。

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