专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20150349091A1 SEMICONDUCTOR POWER DEVICES MANUFACTURED WITH SELF-ALIGNED PROCESSES AND MORE RELIABLE ELECTRICAL CONTACTS 审中-公开
标题翻译：具有自对准工艺和更可靠的电气联系的半导体功率器件
公开(公告)号：US20150349091A1
公开(公告)日：2015-12-03
申请号：US14292880
申请日：2014-05-31
申请人： Hamza Yilmaz , John Chen , Daniel Ng , Wenjun Li
发明人： Hamza Yilmaz , John Chen , Daniel Ng , Wenjun Li
IPC分类号： H01L29/66 , H01L29/40 , H01L29/423
CPC分类号： H01L29/4236 , H01L21/26586 , H01L21/823487 , H01L27/0255 , H01L27/0727 , H01L29/0619 , H01L29/1095 , H01L29/407 , H01L29/4238 , H01L29/4975 , H01L29/66136 , H01L29/66143 , H01L29/665 , H01L29/66666 , H01L29/66674 , H01L29/66734 , H01L29/7804 , H01L29/7806 , H01L29/7811 , H01L29/7813 , H01L29/7827 , H01L29/861 , H01L29/872 , H01L29/8725
摘要： This invention discloses semiconductor power device that includes a plurality of top electrical terminals disposed near a top surface of a semiconductor substrate. Each and every one of the top electrical terminals comprises a terminal contact layer formed as a silicide contact layer near the top surface of the semiconductor substrate. The trench gates of the semiconductor power device are opened from the top surface of the semiconductor substrate and each and every one of the trench gates comprises the silicide layer configured as a recessed silicide contact layer disposed on top of every on of the trench gates slightly below a top surface of the semiconductor substrate surround the trench gate.
摘要翻译：本发明公开了一种半导体功率器件，其包括设置在半导体衬底的顶表面附近的多个顶部电端子。顶部电气端子中的每一个包括在半导体衬底的顶表面附近形成为硅化物接触层的端子接触层。半导体功率器件的沟槽栅极从半导体衬底的顶表面打开，并且每个沟槽栅极包括被配置为硅化物接触层的硅化物层，硅化物层设置在略微低于半导体衬底的顶表面围绕沟槽栅极。

2. 发明授权

US08829603B2 Shielded gate trench MOSFET package 有权
标题翻译：屏蔽栅沟MOSFET封装
公开(公告)号：US08829603B2
公开(公告)日：2014-09-09
申请号：US13212940
申请日：2011-08-18
申请人： Sik Lui , Yi Su , Daniel Ng , Daniel Calafut , Anup Bhalla
发明人： Sik Lui , Yi Su , Daniel Ng , Daniel Calafut , Anup Bhalla
IPC分类号： H01L29/66 , H01L23/64 , H01L29/78 , H01L29/40 , H01L29/423 , H01L23/00
CPC分类号： H01L29/7813 , H01L23/647 , H01L24/06 , H01L24/48 , H01L24/49 , H01L29/407 , H01L29/42368 , H01L29/4238 , H01L29/66734 , H01L29/7803 , H01L29/7811 , H01L2224/0603 , H01L2224/4813 , H01L2224/48247 , H01L2224/4911 , H01L2224/49111 , H01L2924/00014 , H01L2924/10253 , H01L2924/12032 , H01L2924/13091 , H01L2924/3025 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A shielded gate trench field effect transistor can be formed on a substrate having an epitaxial layer on the substrate and a body layer on the epitaxial layer. A trench formed in the body layer and epitaxial layer is lined with a dielectric layer. A shield electrode is formed within a lower portion of the trench. The shield electrode is insulated by the dielectric layer. A gate electrode is formed in the trench above the shield electrode and insulated from the shield electrode by an additional dielectric layer. One or more source regions formed within the body layer is adjacent a sidewall of the trench. A source pad formed above the body layer is electrically connected to the one or more source regions and insulated from the gate electrode and shield electrode. The source pad provides an external contact to the source region. A gate pad provides an external contact to the gate electrode. A shield electrode pad provides an external contact to the shield electrode. A resistive element can be electrically connected between the shield electrode pad and the source lead in the package.
摘要翻译：可以在衬底上具有外延层的衬底上形成屏蔽栅沟槽场效应晶体管，并在外延层上形成体层。形成在体层和外延层中的沟槽衬有介电层。屏蔽电极形成在沟槽的下部内。屏蔽电极由电介质层绝缘。栅极电极形成在屏蔽电极上方的沟槽中，并通过附加的介电层与屏蔽电极绝缘。形成在体层内的一个或多个源极区域与沟槽的侧壁相邻。形成在主体层上方的源极焊盘与一个或多个源极区域电连接并与栅电极和屏蔽电极绝缘。源极焊盘提供与源极区域的外部接触。栅极焊盘提供与栅电极的外部接触。屏蔽电极焊盘提供与屏蔽电极的外部接触。电阻元件可以电连接在封装中的屏蔽电极焊盘和源极引线之间。

3. 发明授权

US08802509B2 Configuration of gate to drain (GD) clamp and ESD protection circuit for power device breakdown protection 有权
标题翻译：门极漏极（GD）钳位和ESD保护电路的配置用于电源器件击穿保护
公开(公告)号：US08802509B2
公开(公告)日：2014-08-12
申请号：US12932584
申请日：2011-02-28
申请人： Yi Su , Anup Bhalla , Daniel Ng
发明人： Yi Su , Anup Bhalla , Daniel Ng
IPC分类号： H01L21/822
CPC分类号： H01L29/7813 , H01L27/0255 , H01L27/0629 , H01L29/0615 , H01L29/0638 , H01L29/0646 , H01L29/0692 , H01L29/0696 , H01L29/66734 , H01L29/7803 , H01L29/7804 , H01L29/7808 , H01L29/7811 , H01L29/7815 , H01L29/8611 , H01L29/866 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor power device supported on a semiconductor substrate comprising a plurality of transistor cells each having a source and a drain with a gate to control an electric current transmitted between the source and the drain. The semiconductor further includes a gate-to-drain (GD) clamp termination connected in series between the gate and the drain further includes a plurality of back-to-back polysilicon diodes connected in series to a silicon diode includes parallel doped columns in the semiconductor substrate wherein the parallel doped columns having a predefined gap. The doped columns further include a U-shaped bend column connect together the ends of parallel doped columns with a deep doped well disposed below and engulfing the U-shaped bend.
摘要翻译：一种半导体功率器件，其被支撑在半导体衬底上，该半导体衬底包括多个晶体管单元，每个晶体管单元具有源极和漏极，栅极用于控制在源极和漏极之间传输的电流。半导体还包括在栅极和漏极之间串联连接的栅极 - 漏极（GD）钳位端接器，还包括串联连接到硅二极管的多个背对背多晶硅二极管，包括半导体中的并行掺杂的列衬底，其中平行掺杂的柱具有预定的间隙。掺杂的柱还包括U形弯曲柱，其将平行掺杂的柱的端部连接在一起，深度掺杂的阱设置在U形弯曲部下方并吞噬U形弯曲部。

4. 发明授权

US08785278B2 Nano MOSFET with trench bottom oxide shielded and third dimensional P-body contact 有权
标题翻译：具有沟槽底部氧化物屏蔽和三维P体接触的纳米MOSFET
公开(公告)号：US08785278B2
公开(公告)日：2014-07-22
申请号：US13364948
申请日：2012-02-02
申请人： Hamza Yilmaz , Daniel Ng , Daniel Calafut , Madhur Bobde , Anup Bhalla , Ji Pan , Yeeheng Lee , Jongoh Kim
发明人： Hamza Yilmaz , Daniel Ng , Daniel Calafut , Madhur Bobde , Anup Bhalla , Ji Pan , Yeeheng Lee , Jongoh Kim
IPC分类号： H01L21/331
CPC分类号： H01L29/7813 , H01L21/26586 , H01L27/088 , H01L29/0623 , H01L29/0626 , H01L29/086 , H01L29/0865 , H01L29/0869 , H01L29/1095 , H01L29/404 , H01L29/407 , H01L29/41766 , H01L29/4236 , H01L29/42368 , H01L29/456 , H01L29/66727 , H01L29/66734 , H01L29/7811
摘要： A semiconductor power device may include a lightly doped layer formed on a heavily doped layer. One or more devices are formed in the lightly doped layer. Each device may include a body region, a source region, and one or more gate electrodes formed in corresponding trenches in the lightly doped region. Each of the trenches has a depth in a first dimension, a width in a second dimension and a length in a third dimension. The body region is of opposite conductivity type to the lightly and heavily doped layers. The source region is formed proximate the upper surface. One or more deep contacts are formed at one or more locations along the third dimension proximate one or more of the trenches. The contacts extend in the first direction from the upper surface into the lightly doped layer and are in electrical contact with the source region.
摘要翻译：半导体功率器件可以包括在重掺杂层上形成的轻掺杂层。在轻掺杂层中形成一个或多个器件。每个器件可以包括主体区域，源极区域和形成在轻掺杂区域中的对应沟槽中的一个或多个栅电极。每个沟槽具有第一维度的深度，第二维度中的宽度和第三维度中的长度。体区与轻掺杂层和重掺杂层具有相反的导电类型。源区域靠近上表面形成。在靠近一个或多个沟槽的第三维度的一个或多个位置处形成一个或多个深触点。触点在第一方向上从上表面延伸到轻掺杂层中并与源区电接触。

5. 发明申请

US20140179074A1 METHOD OF MAKING MOSFET INTEGRATED WITH SCHOTTKY DIODE WITH SIMPLIFIED ONE-TIME TOP-CONTACT TRENCH ETCHING 有权
标题翻译：用肖特基二极管制造MOSFET的方法，具有简单的一次性高度接触式电镀蚀刻
公开(公告)号：US20140179074A1
公开(公告)日：2014-06-26
申请号：US13722930
申请日：2012-12-20
申请人： Ji Pan , Daniel Ng , Sung-Shan Tai , Anup Bhalla
发明人： Ji Pan , Daniel Ng , Sung-Shan Tai , Anup Bhalla
IPC分类号： H01L21/82
CPC分类号： H01L21/26513 , H01L21/2652 , H01L21/26586 , H01L21/82 , H01L21/823412 , H01L27/0629 , H01L29/0638 , H01L29/1095 , H01L29/36 , H01L29/41766 , H01L29/47 , H01L29/4916 , H01L29/66727 , H01L29/66734 , H01L29/7806 , H01L29/7811 , H01L29/7813 , H01L29/872
摘要： Method for fabricating MOSFET integrated with Schottky diode (MOSFET/SKY) is disclosed. Gate trench is formed in an epitaxial layer overlaying semiconductor substrate, gate material is deposited therein. Body, source, dielectric regions are successively formed upon epitaxial layer and the gate trench. Top contact trench (TCT) is etched with vertical side walls defining Schottky diode cross-sectional width SDCW through dielectric and source region defining source-contact depth (SCD); and partially into body region by total body-contact depth (TBCD). A heavily-doped embedded body implant region (EBIR) of body-contact depth (BCD)
摘要翻译：公开了一种用于制造与肖特基二极管（MOSFET / SKY）集成的MOSFET的方法。栅极沟槽形成在覆盖半导体衬底的外延层中，栅极材料沉积在其中。主体，源极，电介质区域依次形成在外延层和栅极沟槽上。通过定义源极接触深度（SCD）的电介质和源极区域，用垂直侧壁蚀刻顶部接触沟槽（TCT），所述垂直侧壁限定肖特基二极管横截面宽度SDCW; 并通过全身接触深度（TBCD）部分进入体区。身体接触深度（BCD）

6. 发明授权

US08748268B1 Method of making MOSFET integrated with schottky diode with simplified one-time top-contact trench etching 有权
标题翻译：使用简化的一次顶接触沟槽蚀刻制作集成肖特基二极管的MOSFET的方法
公开(公告)号：US08748268B1
公开(公告)日：2014-06-10
申请号：US13722930
申请日：2012-12-20
申请人： Ji Pan , Daniel Ng , Sung-Shan Tai , Anup Bhalla
发明人： Ji Pan , Daniel Ng , Sung-Shan Tai , Anup Bhalla
IPC分类号： H01L21/336
CPC分类号： H01L21/26513 , H01L21/2652 , H01L21/26586 , H01L21/82 , H01L21/823412 , H01L27/0629 , H01L29/0638 , H01L29/1095 , H01L29/36 , H01L29/41766 , H01L29/47 , H01L29/4916 , H01L29/66727 , H01L29/66734 , H01L29/7806 , H01L29/7811 , H01L29/7813 , H01L29/872
摘要： Method for fabricating MOSFET integrated with Schottky diode (MOSFET/SKY) is disclosed. Gate trench is formed in an epitaxial layer overlaying semiconductor substrate, gate material is deposited therein. Body, source, dielectric regions are successively formed upon epitaxial layer and the gate trench. Top contact trench (TCT) is etched with vertical side walls defining Schottky diode cross-sectional width SDCW through dielectric and source region defining source-contact depth (SCD); and partially into body region by total body-contact depth (TBCD). A heavily-doped embedded body implant region (EBIR) of body-contact depth (BCD)
摘要翻译：公开了一种用于制造与肖特基二极管（MOSFET / SKY）集成的MOSFET的方法。栅极沟槽形成在覆盖半导体衬底的外延层中，栅极材料沉积在其中。主体，源极，电介质区域依次形成在外延层和栅极沟槽上。通过定义源极接触深度（SCD）的电介质和源极区域，用垂直侧壁蚀刻顶部接触沟槽（TCT），所述垂直侧壁限定肖特基二极管横截面宽度SDCW; 并通过全身接触深度（TBCD）部分进入体区。身体接触深度（BCD）

7. 发明授权

US08643071B2 Integrated snubber in a single poly MOSFET 有权
标题翻译：集成缓冲器在单个多晶硅MOSFET中
公开(公告)号：US08643071B2
公开(公告)日：2014-02-04
申请号：US13517770
申请日：2012-06-14
申请人： Ji Pan , Daniel Ng , Anup Bhalla
发明人： Ji Pan , Daniel Ng , Anup Bhalla
IPC分类号： H01L29/76
CPC分类号： H01L29/7813 , H01L29/0692 , H01L29/0696 , H01L29/41766 , H01L29/7803 , H01L29/7805 , H01L29/94 , H01L29/945 , H01L2924/0002 , H01L2924/00
摘要： A MOSFET device includes one or more active device structures and one or more dummy structures formed from semiconductor drift region and body regions. The dummy structures are electrically connected in parallel to the active device structures. Each dummy structure includes an electrically insulated snubber electrode formed proximate the body region and the drift region, an insulator portion formed over the snubber electrode and a top surface of the body region, and one or more electrical connections between the snubber electrode and portions of the body region and a source electrode. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.
摘要翻译： MOSFET器件包括一个或多个有源器件结构和由半导体漂移区域和主体区域形成的一个或多个虚设结构。虚拟结构与有源器件结构并联电连接。每个虚拟结构包括在主体区域和漂移区域附近形成的电绝缘缓冲电极，形成在缓冲电极上的绝缘体部分和身体区域的顶表面，以及缓冲电极和部分之间的一个或多个电连接体区和源电极。要强调的是，提供这个摘要是为了符合要求摘要的规则，允许搜索者或其他读者快速确定技术公开内容的主题。提交它的理解是，它不会用于解释或限制权利要求的范围或含义。

8. 发明申请

US20130334599A1 INTEGRATED SNUBBER IN A SINGLE POLY MOSFET 有权
标题翻译：集成SNUBBER在单个POLYMOSFET
公开(公告)号：US20130334599A1
公开(公告)日：2013-12-19
申请号：US13517770
申请日：2012-06-14
申请人： Ji Pan , Daniel Ng , Anup Bhalla
发明人： Ji Pan , Daniel Ng , Anup Bhalla
IPC分类号： H01L27/088 , H01L21/8232
CPC分类号： H01L29/7813 , H01L29/0692 , H01L29/0696 , H01L29/41766 , H01L29/7803 , H01L29/7805 , H01L29/94 , H01L29/945 , H01L2924/0002 , H01L2924/00
摘要： A MOSFET device includes one or more active device structures and one or more dummy structures formed from semiconductor drift region and body regions. The dummy structures are electrically connected in parallel to the active device structures. Each dummy structure includes an electrically insulated snubber electrode formed proximate the body region and the drift region, an insulator portion formed over the snubber electrode and a top surface of the body region, and one or more electrical connections between the snubber electrode and portions of the body region and a source electrode. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.
摘要翻译： MOSFET器件包括一个或多个有源器件结构和由半导体漂移区域和主体区域形成的一个或多个虚设结构。虚拟结构与有源器件结构并联电连接。每个虚拟结构包括在主体区域和漂移区域附近形成的电绝缘缓冲电极，形成在缓冲电极上的绝缘体部分和身体区域的顶表面，以及缓冲电极和部分之间的一个或多个电连接体区和源电极。要强调的是，提供这个摘要是为了符合要求摘要的规则，允许搜索者或其他读者快速确定技术公开内容的主题。提交它的理解是，它不会用于解释或限制权利要求的范围或含义。

9. 发明授权

US08502302B2 Integrating Schottky diode into power MOSFET 有权
标题翻译：将肖特基二极管集成到功率MOSFET中
公开(公告)号：US08502302B2
公开(公告)日：2013-08-06
申请号：US13098852
申请日：2011-05-02
申请人： Yi Su , Daniel Ng , Anup Bhalla , Hong Chang , Jongoh Kim , John Chen
发明人： Yi Su , Daniel Ng , Anup Bhalla , Hong Chang , Jongoh Kim , John Chen
IPC分类号： H01L27/06 , H01L21/336
CPC分类号： H01L29/7801 , H01L21/26586 , H01L29/0623 , H01L29/0696 , H01L29/0891 , H01L29/407 , H01L29/41766 , H01L29/42368 , H01L29/4238 , H01L29/47 , H01L29/4933 , H01L29/66719 , H01L29/66727 , H01L29/66734 , H01L29/78 , H01L29/7806 , H01L29/7811 , H01L29/7813 , H01L29/782 , H01L29/872
摘要： A semiconductor device includes a plurality of trenches including active gate trenches in an active area and gate runner/termination trenches and shield electrode pickup trenches in a termination area outside the active area. The gate runner/termination trenches include one or more trenches that define a mesa located outside an active area. A first conductive region is formed in the plurality of trenches. An intermediate dielectric region and termination protection region are formed in the trenches that define the mesa. A second conductive region is formed in the portion of the trenches that define the mesa. The second conductive region is electrically isolated from the first conductive region by the intermediate dielectric region. A first electrical contact is made to the second conductive regions and a second electrical contact to the first conductive region in the shield electrode pickup trenches. One or more Schottky diodes are formed within the mesa.
摘要翻译：半导体器件包括多个沟槽，包括有源区域中的有源栅极沟槽和栅极流道/终止沟槽以及在有源区域外部的终止区域中的屏蔽电极拾取沟槽。栅极流道/终止沟槽包括限定位于有源区域之外的台面的一个或多个沟槽。在多个沟槽中形成第一导电区域。在限定台面的沟槽中形成中间介质区域和端接保护区域。在限定台面的沟槽部分中形成第二导电区域。第二导电区域通过中间介电区域与第一导电区域电隔离。对第二导电区域进行第一电接触，并且在屏蔽电极拾取沟槽中对第一导电区域进行第二电接触。在台面内形成一个或多个肖特基二极管。

10. 发明授权

US08362585B1 Junction barrier Schottky diode with enforced upper contact structure and method for robust packaging 有权
标题翻译：具有强制上接触结构的结型势垒肖特基二极管和坚固封装的方法
公开(公告)号：US08362585B1
公开(公告)日：2013-01-29
申请号：US13184488
申请日：2011-07-15
申请人： Anup Bhalla , Ji Pan , Daniel Ng
发明人： Anup Bhalla , Ji Pan , Daniel Ng
IPC分类号： H01L29/66 , H01L29/40 , H01L21/02
CPC分类号： H01L29/872 , H01L24/05 , H01L29/0619 , H01L29/417 , H01L2924/01029 , H01L2924/12032 , H01L2924/00
摘要： A semiconductor junction barrier Schottky (JBS-SKY) diode with enforced upper contact structure (EUCS) is disclosed. Referencing an X-Y-Z coordinate, the JBS-SKY diode has semiconductor substrate (SCST) parallel to X-Y plane. Active device zone (ACDZ) atop SCST and having a JBS-SKY diode with Z-direction current flow. Peripheral guarding zone (PRGZ) atop SCST and surrounding the ACDZ. The ACDZ has active lower semiconductor structure (ALSS) and enforced active upper contact structure (EUCS) atop ALSS. The EUC has top contact metal (TPCM) extending downwards and in electrical conduction with bottom of EUCS; and embedded bottom supporting structure (EBSS) inside TPCM and made of a hard material, the EBSS extending downwards till bottom of the EUCS. Upon encountering bonding force onto TPCM during packaging of the JBS-SKY diode, the EBSS enforces the EUCS against an otherwise potential micro cracking of the TPCM degrading the leakage current of the JBS-SKY diode.
摘要翻译：公开了一种具有强制上接触结构（EUCS）的半导体结屏障肖特基（JBS-SKY）二极管。参考X-Y-Z坐标，JBS-SKY二极管具有与X-Y平面平行的半导体衬底（SCST）。有源器件区（ACDZ）位于SCST上方，并具有Z方向电流流动的JBS-SKY二极管。外围防护区（PRGZ）在SCST顶部并围绕ACDZ。 ACDZ在ALSS顶部具有活性较低的半导体结构（ALSS）和强制性的上接触结构（EUCS）。 EUC具有向下延伸并与EUCS底部导电的顶部接触金属（TPCM）; 并在TPCM内部嵌入底部支撑结构（EBSS），由硬质材料制成，EBSS向下延伸至EUCS底部。在JBS-SKY二极管封装期间遇到TPCM上的结合力时，EBSS强制EUCS抵抗TPCM的另外潜在的微裂纹，降低JBS-SKY二极管的漏电流。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式