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1. 发明申请

US20080072205A1 Method and apparatus for designing a logic circuit using one or more circuit elements having a substantially continuous range of values 审中-公开
标题翻译：使用具有基本连续的值范围的一个或多个电路元件设计逻辑电路的方法和装置
公开(公告)号：US20080072205A1
公开(公告)日：2008-03-20
申请号：US11522733
申请日：2006-09-18
申请人： Edward B. Harris , Cynthia C. Lee , Gerard Zaneski
发明人： Edward B. Harris , Cynthia C. Lee , Gerard Zaneski
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： Methods and apparatus are provided for designing a logic circuit using one or more circuit elements having a substantially continuous range of values. A circuit is designed based on a functional description of the circuit and one or more circuit constraints. The circuit is initially designed using a library of discrete circuit element options. The initial circuit design is evaluated to determine whether one or more discrete circuit elements cause the circuit to not satisfy the one or more circuit constraints, such as power, area or timing requirements for the circuit. At least one replacement circuit element is generated that has at least one cell parameter configured such that the at least one replacement circuit element will have a performance characteristic that allows the circuit to satisfy the one or more circuit constraints. The at least one cell parameter for the at least one replacement circuit element is configurable so that the performance characteristic can be selectable from a substantially continuous range of values. The at least one of the discrete circuit elements is replaced in the circuit with at least one of the replacement circuit elements.
摘要翻译：提供了使用具有基本上连续的值范围的一个或多个电路元件设计逻辑电路的方法和装置。基于电路的功能描述和一个或多个电路约束来设计电路。该电路最初使用分立电路元件选项库进行设计。评估初始电路设计以确定一个或多个分立电路元件是否导致电路不满足一个或多个电路约束，例如电路的功率，面积或时序要求。产生至少一个替换电路元件，其具有被配置为使得至少一个替换电路元件具有允许电路满足一个或多个电路约束的性能特性的至少一个单元参数。用于至少一个替换电路元件的至少一个电池参数是可配置的，使得性能特征可以从基本连续的值范围中选择。至少一个离散电路元件在电路中被替换为至少一个替换电路元件。

2. 发明授权

US07633152B2 Heat dissipation in integrated circuits 有权
标题翻译：集成电路中的散热
公开(公告)号：US07633152B2
公开(公告)日：2009-12-15
申请号：US11468901
申请日：2006-08-31
申请人： Cynthia C. Lee , Sidhartha Sen
发明人： Cynthia C. Lee , Sidhartha Sen
IPC分类号： H01L23/10
CPC分类号： H01L23/367 , H01L23/3677 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides an integrated circuit and method of manufacture therefore. The integrated circuit, in one embodiment, includes heat conducting elements located proximate a plurality of heat generating components located over a substrate. The integrated circuit may further include a heat radiating element comprising one or more fins in thermal communication and physical contact with the heat conducting elements, the heat radiating element configured to dissipate heat generated by the heat generating components away from the integrated circuit.
摘要翻译：本发明提供一种集成电路及其制造方法。在一个实施例中，集成电路包括靠近位于衬底上方的多个发热部件的导热元件。集成电路还可以包括散热元件，该散热元件包括与热传导元件热连通并物理接触的一个或多个翅片，该散热元件被配置为将由发热元件产生的热量散发离开集成电路。

3. 发明授权

US06985229B2 Overlay metrology using scatterometry profiling 失效
公开(公告)号：US06985229B2
公开(公告)日：2006-01-10
申请号：US10158775
申请日：2002-05-30
申请人： Cynthia C. Lee , Stephen Arlon Meisner , Thomas Michael Wolf , Alberto Santoni , John Martin McIntosh
发明人： Cynthia C. Lee , Stephen Arlon Meisner , Thomas Michael Wolf , Alberto Santoni , John Martin McIntosh
IPC分类号： G01B11/00 , G01R31/26 , H01L21/66
CPC分类号： G03F7/70633 , G01B11/272
摘要： A method for nondestructively characterizing alignment overlay between two layers of a semiconductor wafer. An incident beam of radiation is directed upon the wafer surface and the properties of the resulting diffracted beam are determined, in one embodiment as a function of wavelength or incident angle. The spectrally or angularly resolved characteristics of the diffracted beam are related to the alignment of the overlay features. A library of calculated diffraction spectra is established by modeling a full range of expected variations in overlay alignment. The spectra resulting from the inspection of an actual wafer having alignment targets in at least two layers is compared against the library to identify a best fit to characterize the actual alignment. The results of the comparison may be used as an input for upstream and/or downstream process control.

4. 发明授权

US06284598B1 Method of manufacturing a flash memory cell having inter-poly-dielectric isolation 有权
标题翻译：制造具有多晶硅绝缘隔离的闪存单元的方法
公开(公告)号：US06284598B1
公开(公告)日：2001-09-04
申请号：US09447893
申请日：1999-11-23
申请人： Patrick J. Kelley , Ranbir Singh , Larry B. Fritzinger , Cynthia C. Lee , John Simon Molloy
发明人： Patrick J. Kelley , Ranbir Singh , Larry B. Fritzinger , Cynthia C. Lee , John Simon Molloy
IPC分类号： H01L31336
CPC分类号： H01L27/11521 , H01L27/115
摘要： A method of forming round corners for a gate oxide between a floating gate and a control gate of a memory cell comprises the steps of forming the floating gate over a tunnel oxide; forming a mask over the floating gate; forming rounded end caps adjacent distal ends of the mask; transferring the rounding of the end caps to top corners of the floating gate; forming the gate oxide over the floating gate; and, forming the control gate over the gate oxide. A memory cell having a rounded corner interface between the floating gate and control gate is also provided.
摘要翻译：在存储单元的浮动栅极和控制栅极之间形成用于栅极氧化物的圆角的方法包括在隧道氧化物上形成浮置栅极的步骤; 在浮动门上形成掩模; 在所述掩模的远端附近形成圆形端盖; 将端盖的四舍五入转移到浮动门的顶角; 在浮栅上形成栅极氧化物; 并且在栅极氧化物上形成控制栅极。还提供了在浮动栅极和控制栅极之间具有圆角接合的存储单元。

5. 发明授权

US06197699B1 In situ dry cleaning process for poly gate etch 失效
标题翻译：多栅极蚀刻的原位干洗工艺
公开(公告)号：US06197699B1
公开(公告)日：2001-03-06
申请号：US09009399
申请日：1998-01-20
申请人： Larry B. Fritzinger , Cynthia C. Lee , Edward M. Middlebrook , John M. Sniegowski
发明人： Larry B. Fritzinger , Cynthia C. Lee , Edward M. Middlebrook , John M. Sniegowski
IPC分类号： H01H100
CPC分类号： H01J37/32862 , H01L21/3065
摘要： The present invention provides a method for cleaning a contaminated chamber used in the manufacture of semiconductor devices. In one embodiment, the method comprises the steps of injecting, under pressure, a gas mixture of a fluorine-containing gas and an inert gas into the contaminated chamber, radiating the contaminated chamber with a radio frequency during the step of injecting, and removing volatile by-products or solid particulates from the contaminated chamber by performing pump-purge cycles within the contaminated chamber.
摘要翻译：本发明提供了一种清洁用于制造半导体器件的污染室的方法。在一个实施方案中，该方法包括以下步骤：在压力下将含氟气体和惰性气体的气体混合物注入到污染室中，在注入步骤期间以射频辐射污染室，并除去挥发性通过在受污染的室内进行泵清洗循环，从受污染的室中产生副产物或固体颗粒物。

6. 发明授权

US06174786B1 Shallow trench isolation method providing rounded top trench corners 有权
标题翻译：浅沟槽隔离方法提供圆顶顶沟
公开(公告)号：US06174786B1
公开(公告)日：2001-01-16
申请号：US09447154
申请日：1999-11-23
申请人： Patrick J. Kelley , Ranbir Singh , Larry B. Fritzinger , Cynthia C. Lee , John Simon Molloy
发明人： Patrick J. Kelley , Ranbir Singh , Larry B. Fritzinger , Cynthia C. Lee , John Simon Molloy
IPC分类号： H01L2176
CPC分类号： H01L21/76232
摘要： A method of shallow trench isolation by forming a trench in a semiconductor device comprises the steps of forming an oxide layer; forming a mask layer; anisotropically etching the mask layer; forming a second oxide layer; forming a cap layer; forming rounded end caps adjacent the mask; and transferring the rounding of the caps to the top corners of the trench. The oxide layer is formed over a substrate of the semiconductor device. The mask layer is formed over the oxide layer. The mask layer is then anisotropically etched to form the mask and an opening in the mask. The opening in the mask exposes the substrate, and the width of the opening is greater than the width of the trench. Blanket etching the cap layer forms the rounded end caps. The rounded end caps are adjacent to the mask on opposite ends of the opening, and the distance between the end caps is about equal to the width of the trench. The trench is formed by plasma etching the trench. During this process, the rounding of the end caps is transferred to the top corners of a trench.
摘要翻译：通过在半导体器件中形成沟槽来进行浅沟槽隔离的方法包括以下步骤：形成氧化物层; 形成掩模层; 各向异性地蚀刻掩模层; 形成第二氧化物层; 形成盖层; 在掩模附近形成圆形端盖; 并且将盖的四舍五入转移到沟槽的顶角。氧化物层形成在半导体器件的衬底上。掩模层形成在氧化物层的上方。然后对掩模层进行各向异性蚀刻以形成掩模和掩模中的开口。掩模中的开口露出衬底，并且开口的宽度大于沟槽的宽度。蚀刻盖层的毯子形成圆形端盖。圆形端盖在开口的相对端与掩模相邻，并且端盖之间的距离大约等于沟槽的宽度。通过等离子体蚀刻沟槽形成沟槽。在此过程中，端盖的四舍五入转移到沟槽的顶角。

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