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1. 发明授权

US5729767A System and method for accessing peripheral devices on a non-functional controller 失效
标题翻译：用于访问非功能控制器上的外围设备的系统和方法
公开(公告)号：US5729767A
公开(公告)日：1998-03-17
申请号：US319689
申请日：1994-10-07
申请人： Craig S. Jones , Victor K. Pecone , Jay Lory
发明人： Craig S. Jones , Victor K. Pecone , Jay Lory
IPC分类号： G06F11/00 , G06F11/20 , G06F11/22 , G06F11/267 , G06F11/34 , G06F13/00
CPC分类号： G06F11/1433 , G06F11/073 , G06F11/0745 , G06F11/0781 , G06F11/22 , G06F11/2236 , G06F11/006 , G06F11/2205 , G06F11/3476
摘要： A computer system including a host CPU, a primary PCI bus coupled to the CPU, and a bus adapter coupled to the primary PCI bus, wherein the host CPU can access peripherals comprised in the bus adapter even when the bus adapter is inoperable. The bus adapter includes a PCI to PCI interface controller which includes a primary PCI interface for coupling to the primary PCI bus and a secondary PCI interface bridge for coupling to a secondary PCI bus. Peripheral bus interface logic is coupled between the primary PCI interface and the secondary PCI interface, and this interface logic couples to various peripheral devices, including ROM/Flash memory and non-volatile static random access memory (NVSRAM). According to the present invention, a host utility executing on the CPU can access the peripheral devices without having to access the secondary PCI bus. Thus, if the secondary PCI bus becomes inoperable or the local processor is unable to boot, the host can still access the memory in the peripheral devices because the peripheral interface is effectively decoupled from the secondary PCI bus and the local processor. The present invention includes a host utility which can update the Flash memory, thereby providing a cost-effective and efficient mechanism for restoring code in a corrupted Flash device on a failed board. This also enables the Flash memory to be programmed for the first time during manufacturing. The system and method of the present invention allows the host CPU to access the NVRAM to obtain event failure information even if the secondary PCI bus has failed.
摘要翻译：包括主机CPU，耦合到CPU的主PCI总线和耦合到主PCI总线的总线适配器的计算机系统，其中即使总线适配器不可操作，主机CPU也可以访问包含在总线适配器中的外围设备。总线适配器包括PCI至PCI接口控制器，其包括用于耦合到主PCI总线的主PCI接口和用于耦合到辅助PCI总线的辅助PCI接口桥。外部总线接口逻辑耦合在主PCI接口和辅助PCI接口之间，并且该接口逻辑耦合到各种外围设备，包括ROM /闪存和非易失性静态随机存取存储器（NVSRAM）。根据本发明，在CPU上执行的主机实用程序可以访问外围设备，而不必访问辅助PCI总线。因此，如果辅助PCI总线变得不可操作或本地处理器无法引导，则主机仍然可以访问外围设备中的存储器，因为外围接口有效地与辅助PCI总线和本地处理器分离。本发明包括可以更新闪存的主机实用程序，从而提供用于在故障板上的损坏的闪存设备中恢复代码的成本有效且有效的机制。这也使得在制造过程中首次对闪存进行编程。本发明的系统和方法允许主机CPU访问NVRAM以获得事件故障信息，即使辅助PCI总线发生故障。

2. 发明授权

US5619728A Decoupled DMA transfer list storage technique for a peripheral resource controller 失效
标题翻译：用于外围资源控制器的去耦DMA传输列表存储技术
公开(公告)号：US5619728A
公开(公告)日：1997-04-08
申请号：US326570
申请日：1994-10-20
申请人： Craig S. Jones , Jay Lory , Victor K. Pecone
发明人： Craig S. Jones , Jay Lory , Victor K. Pecone
IPC分类号： G06F13/28 , H01J3/00
CPC分类号： G06F13/28
摘要： A peripheral resource controller such as a caching disk array controller is provided for controlling the transfer of data between a host bus and a peripheral resource, such as an array of hard disk drives. The peripheral resource controller includes a bus interface controller for providing an interface between the host bus and a local bus of the peripheral controller. The bus interface controller further includes a peripheral bus interface which accommodates accesses to a peripheral bus and a DMA controller for controlling direct memory access operations between a local memory of the peripheral controller and a system memory of the host computer. A DMA transfer list memory is coupled to the peripheral bus for storing DMA transfer information. The DMA controller fetches host and local address as well as block size information from the DMA transfer list memory to thereby effectuate DMA operations. In one specific implementation, a local processor of the peripheral controller loads the DMA transfer information into the DMA transfer list memory by causing the execution of one or more memory write cycles on the local bus. A local bus interface of the bus interface controller responds as a target and routes the data to a peripheral bus interface. The peripheral bus interface, which functions as a master of the peripheral bus, responsively effectuates corresponding cycles on the peripheral bus to write the DMA transfer information into the DMA transfer list memory.
摘要翻译：提供诸如缓存磁盘阵列控制器之类的外围资源控制器，用于控制主机总线与诸如硬盘驱动器阵列的外围资源之间的数据传输。外围资源控制器包括总线接口控制器，用于在主机总线和外围控制器的本地总线之间提供接口。总线接口控制器还包括外围总线接口，其适应对外围总线的访问和用于控制外围控制器的本地存储器与主计算机的系统存储器之间的直接存储器访问操作的DMA控制器。 DMA传输列表存储器耦合到外围总线以存储DMA传输信息。 DMA控制器从DMA传输列表存储器中获取主机和本地地址以及块大小信息，从而实现DMA操作。在一个具体实现中，外围控制器的本地处理器通过在本地总线上执行一个或多个存储器写周期来将DMA传输信息加载到DMA传输列表存储器中。总线接口控制器的本地总线接口作为目标进行响应，并将数据路由到外设总线接口。用作外设总线主机的外设总线接口响应于外设总线上的相应周期，将DMA传输信息写入DMA传输列表存储器。

3. 发明授权

US5619723A System for scheduling read ahead operations if new request is sequential of last n last read requests wherein n is different on independent activities 失效
标题翻译：用于调度预读操作的系统，如果新请求是最后n个最后读取请求的顺序，其中n在独立活动上不同
公开(公告)号：US5619723A
公开(公告)日：1997-04-08
申请号：US562238
申请日：1995-11-21
申请人： Craig S. Jones , Kenneth L. Jeffries , Terry J. Parks
发明人： Craig S. Jones , Kenneth L. Jeffries , Terry J. Parks
IPC分类号： G06F3/06 , G06F12/08 , G11B20/18 , G06F13/14
CPC分类号： G06F3/0601 , G06F12/0862 , G11B20/1833 , G11B20/1883 , G06F12/0866 , G06F2003/0697 , G06F2212/6026 , G11B2220/20
摘要： A disk drive array with a controller which provides: dynamic remapping for grown defects in the disk drives, multi-thread request processing with a variable number of forkings, defect tracking with both logical and physical lists, guarded writes of less than a full stripe optimized by selectably using the redundancy to limit the number of sectors involved, association of multiple operations with a single disk request in order to facilitate error handling, use of an access hiatus as indication of further opportunity to rebuild data in background, and scatter/scatter (bidirectional scatter/gather) operations.
摘要翻译：具有控制器的磁盘驱动器阵列，其提供：用于磁盘驱动器中的长期缺陷的动态重映射，具有可变数量的分叉的多线程请求处理，具有逻辑和物理列表的缺陷跟踪，小于全条带优化的保护写入通过可选择地使用冗余来限制涉及的扇区数量，多个操作与单个磁盘请求的关联以便于错误处理，使用访问间隙作为在后台重建数据的进一步机会的指示以及散射/散射（双向分散/聚合）操作。

4. 发明授权

US5572660A System and method for selective write-back caching within a disk array subsystem 失效
标题翻译：在磁盘阵列子系统中选择性回写缓存的系统和方法
公开(公告)号：US5572660A
公开(公告)日：1996-11-05
申请号：US557671
申请日：1995-11-13
申请人： Craig S. Jones
发明人： Craig S. Jones
IPC分类号： G06F11/10 , G06F12/16
CPC分类号： G06F12/0804 , G06F11/1076 , G06F2211/1009
摘要： A fault tolerant disk array subsystem is provided that includes a plurality of data drives for storing real data and a parity drive for storing redundant data. Each data drive is associated with a dedicated write-through cache unit and the parity drive is associated with a dedicated write-back cache unit. An array scheduler schedules read and write operations to access the data drives and includes a parity control unit for updating parity information when new data is written to one of the data drives. Since a write-back caching technique is used to store updated parity information, the write latency of the parity drive does not limit the write-throughput of the disk array subsystem. Furthermore, since a non-volatile memory unit is provided to store the addresses of any dirty parity information within the write-back cache unit, parity information can be reconstructed in the event of a power failure. The disk array subsystem provides a low cost, mass storage resource having improved write performance characteristics. The disk array subsystem also accommodates data redundancy to allow data restoration in the event of disk failure.
摘要翻译：提供了一种容错磁盘阵列子系统，其包括用于存储实际数据的多个数据驱动器和用于存储冗余数据的奇偶校验驱动器。每个数据驱动器与专用的直写缓存单元相关联，并且奇偶校验驱动器与专用回写高速缓存单元相关联。阵列调度器调度读取和写入操作以访问数据驱动器，并且包括奇偶校验控制单元，用于当将新数据写入数据驱动器之一时更新奇偶校验信息。由于使用回写高速缓存技术来存储更新的奇偶校验信息，所以奇偶校验驱动器的写入延迟并不限制磁盘阵列子系统的写入吞吐量。此外，由于提供非易失性存储器单元来存储写回高速缓存单元内的任何脏奇偶校验信息的地址，所以在电源故障的情况下可以重建奇偶校验信息。磁盘阵列子系统提供了具有改进的写性能特性的低成本大容量存储资源。磁盘阵列子系统还适应数据冗余，以便在发生磁盘故障时恢复数据。

5. 发明授权

US5548783A Composite drive controller including composite disk driver for supporting composite drive accesses and a pass-through driver for supporting accesses to stand-alone SCSI peripherals 失效
标题翻译：复合驱动器控制器包括用于支持复合驱动器访问的复合磁盘驱动器和用于支持对独立SCSI外设的访问的直通驱动器
公开(公告)号：US5548783A
公开(公告)日：1996-08-20
申请号：US145008
申请日：1993-10-28
申请人： Craig S. Jones , Alan Davis
发明人： Craig S. Jones , Alan Davis
IPC分类号： G06F3/06 , G06F13/10 , G06F11/16 , G06F15/16
CPC分类号： G06F3/0601 , G06F13/105 , G06F2003/0692
摘要： A drive array controller is provided that serves as an interface between both stand-alone SCSI devices as well as SCSI devices that form a composite drive. Since an AHA emulation interface is incorporated on the drive array controller, the drive array controller is compatible with conventional AHA device drivers that drive stand-alone peripheral devices such as SCSI CD-ROM units and SCSI tape drives. The drive array controller includes a SCSI pass-through driver that extracts a SCSI command descriptor block from a command control block created by the AHA device driver. The drive array controller further provides a separate peripheral access channel to support high speed composite drive operations through a composite device driver. Since the AHA emulation interface and a composite drive interface are provided on a common peripheral board, only one EISA expansion slot is occupied.
摘要翻译：提供的驱动器阵列控制器用作两个独立SCSI设备之间的接口以及形成复合驱动器的SCSI设备。由于AHA仿真接口被并入驱动器阵列控制器，因此驱动器阵列控制器与传统的AHA设备驱动程序兼容，驱动器可以驱动SCSI CD-ROM单元和SCSI磁带驱动器等独立的外围设备。驱动器阵列控制器包括从由AHA设备驱动器创建的命令控制块提取SCSI命令描述符块的SCSI直通驱动器。驱动器阵列控制器还提供单独的外围设备访问通道，以通过复合设备驱动器来支持高速复合驱动操作。由于在公共外设板上提供了AHA仿真接口和复合驱动接口，因此只占用一个EISA扩展槽。

6. 发明授权

US6050040A Decorative anti slip floor covering 失效
标题翻译：装饰防滑地板
公开(公告)号：US6050040A
公开(公告)日：2000-04-18
申请号：US146572
申请日：1998-09-03
申请人： Craig S. Jones
发明人： Craig S. Jones
IPC分类号： B32B3/24 , E01C5/22 , E04F15/02 , E04F15/06 , E04F13/00
CPC分类号： B32B3/266 , E01C5/22 , E04F15/02 , E04F15/06
摘要： A tile for superposition over a horizontal floor comprises a thin flat metal plate of uniform thickness with a plurality of apertures extending laterally therethrough in spaced relation to one another and to the edges of thereof and having a non-metallic insert in each of the apertures of a thickness less than the thickness of the metal portion of the tile and having an upper surface disposed below the upper surface of the metal portion of the tile.
摘要翻译：用于在水平地板上叠加的瓦片包括具有均匀厚度的薄平板金属板，具有多个孔，其横向延伸穿过其间彼此间隔开并且与其边缘间隔开，并且在每个孔中具有非金属插入物厚度小于瓦片的金属部分的厚度，并且具有设置在瓦片的金属部分的上表面下方的上表面。

7. 发明授权

US5911084A System and method for accessing peripheral devices on a non-functional controller 失效
标题翻译：用于访问非功能控制器上的外围设备的系统和方法
公开(公告)号：US5911084A
公开(公告)日：1999-06-08
申请号：US24719
申请日：1998-02-17
申请人： Craig S. Jones , Victor K. Pecone , Jay Lory
发明人： Craig S. Jones , Victor K. Pecone , Jay Lory
IPC分类号： G06F11/00 , G06F11/20 , G06F11/22 , G06F11/267 , G06F11/34 , G06F13/00
CPC分类号： G06F11/1433 , G06F11/073 , G06F11/0745 , G06F11/0781 , G06F11/22 , G06F11/2236 , G06F11/006 , G06F11/2205 , G06F11/3476
摘要： A computer system including a host CPU, a primary PCI bus coupled to the CPU, and a bus adapter coupled to the primary PCI bus, wherein the host CPU can access peripherals comprised in the bus adapter even when the bus adapter is inoperable. The bus adapter includes a PCI to PCI interface controller which includes a primary PCI interface for coupling to the primary PCI bus and a secondary PCI interface bridge for coupling to a secondary PCI bus. Peripheral bus interface logic is coupled between the primary PCI interface and the secondary PCI interface, and this interface logic couples to various peripheral devices, including ROM/Flash memory and non-volatile static random access memory (NVSRAM). According to the present invention, a host utility executing on the CPU can access the peripheral devices without having to access the secondary PCI bus. Thus, if the secondary PCI bus becomes inoperable or the local processor is unable to boot the host can still access the memory in the peripheral devices because the peripheral interface is effectively decoupled from the secondary PCI bus and the local processor. The present invention includes a host utility which can update the Flash memory, thereby providing a cost-effective and efficient mechanism for restoring code in a corrupted Flash device on a failed board. This also enables the Flash memory to be programmed for the first time during manufacturing. The system and method of the present invention allows the host CPU to access the NVRAM to obtain event failure information even if the secondary PCI bus has failed.
摘要翻译：包括主机CPU，耦合到CPU的主PCI总线和耦合到主PCI总线的总线适配器的计算机系统，其中即使总线适配器不可操作，主机CPU也可以访问包含在总线适配器中的外围设备。总线适配器包括PCI至PCI接口控制器，其包括用于耦合到主PCI总线的主PCI接口和用于耦合到辅助PCI总线的辅助PCI接口桥。外部总线接口逻辑耦合在主PCI接口和辅助PCI接口之间，并且该接口逻辑耦合到各种外围设备，包括ROM /闪存和非易失性静态随机存取存储器（NVSRAM）。根据本发明，在CPU上执行的主机实用程序可以访问外围设备，而不必访问辅助PCI总线。因此，如果辅助PCI总线变得不可操作或本地处理器无法引导，则主机仍然可以访问外围设备中的存储器，因为外围接口有效地从辅助PCI总线和本地处理器分离。本发明包括可以更新闪存的主机实用程序，从而提供用于在故障板上的损坏的闪存设备中恢复代码的成本有效且有效的机制。这也使得在制造过程中首次对闪存进行编程。本发明的系统和方法允许主机CPU访问NVRAM以获得事件故障信息，即使辅助PCI总线发生故障。

8. 发明授权

US5805880A Operating system independent method for avoiding operating system security for operations performed by essential utilities 失效
标题翻译：操作系统独立的方法，用于避免基本实用程序执行操作的操作系统安全性
公开(公告)号：US5805880A
公开(公告)日：1998-09-08
申请号：US592501
申请日：1996-01-26
申请人： John J. Pearce , Craig S. Jones
发明人： John J. Pearce , Craig S. Jones
IPC分类号： G06F9/38 , G06F9/445 , G06F21/00 , G06F9/06
CPC分类号： G06F9/3877 , G06F21/80 , G06F9/4401 , G06F2211/1097
摘要： An essential utility routine accesses a protected computer system component by making a call to a coprocessor that performs a desired function to avoid security measures imposed by an operating system. Various suitable coprocessors include an additional coprocessor connected to a host processor running the operating system imposing the security measures such as a coprocessor on a add-in card to a computer system, a microcontroller, or a system management mode (SMM) program running on the host processor. The essential utility operates on a computer system having a processor operating under an operating system and a storage. The operating system includes software which limits access to the storage. The utility includes a coprocessor, a software interface and a utility routine. The coprocessor is connected to the storage and operative independent of the operating system for accessing the storage. The software interface is connected to the coprocessor and executes on the processor to control input and output operations on the processor. The utility routine executes on the processor and includes a program code operative via the software interface for activating the coprocessor to access the storage and receiving a response from the coprocessor.
摘要翻译：基本实用程序例程通过调用执行所需功能的协处理器来访问受保护的计算机系统组件，以避免操作系统施加的安全措施。各种合适的协处理器包括连接到主机处理器的附加协处理器，该主机处理器将运行操作系统的安全措施（例如，附加卡上的协处理器）运行到计算机系统，微控制器或在其上运行的系统管理模式（SMM）主机处理器基本实用程序在具有在操作系统和存储器下操作的处理器的计算机系统上运行。操作系统包括限制对存储的访问的软件。该实用程序包括协处理器，软件接口和实用程序。协处理器连接到存储器并独立于操作系统操作以访问存储器。软件接口连接到协处理器，并在处理器上执行以控制处理器上的输入和输出操作。该实用程序程序在处理器上执行并且包括通过软件接口操作的程序代码，用于激活协处理器以访问存储器并从协处理器接收响应。

9. 发明授权

US5664119A Local proactive hot swap request/acknowledge system 失效
标题翻译：本地主动热插拔请求/确认系统
公开(公告)号：US5664119A
公开(公告)日：1997-09-02
申请号：US699016
申请日：1996-08-16
申请人： Kenneth L. Jeffries , Craig S. Jones , Victor K. Pecone
发明人： Kenneth L. Jeffries , Craig S. Jones , Victor K. Pecone
IPC分类号： G06F13/40 , G06F13/00
CPC分类号： G06F13/4081
摘要： Apparatus and method for implementing a local proactive hot plug request/acknowledge scheme is disclosed. In a preferred embodiment, each hot pluggable device installable on a computer bus, such as a SCSI bus, is provided with a physical user interface comprising a mechanical request initiator, such as a button or two-position switch, for allowing a user to generate a hot swap request to a controller associated with the bus prior to actual installation of the device on, or removal of the device from, the bus. Upon receipt of the request, the controller determines whether the requested action may be performed, provides a visual indication of its determination to the user via an LED on the user interface and, if installation or removal is determined to be prudent, performs the hot installation/removal in an orderly manner so as not to adversely affect ongoing system operations.
摘要翻译：公开了用于实现本地主动式热插拔请求/确认方案的装置和方法。在优选实施例中，可安装在诸如SCSI总线的计算机总线上的每个热插拔设备都设置有物理用户界面，其包括诸如按钮或两位置开关的机械请求发起者，用于允许用户生成在将设备实际安装在总线上或从总线移除设备之前，向与总线相关联的控制器的热交换请求。在接收到请求时，控制器确定是否可以执行请求的动作，通过用户界面上的LED向用户提供其确定的可视指示，并且如果确定安全或删除是谨慎的，则执行热安装 /有秩序地移除，以免对正在进行的系统操作产生不利影响。

10. 发明授权

US5623700A Interface circuit having zero latency buffer memory and cache memory information transfer 失效
标题翻译：接口电路具有零延迟缓冲存储器和高速缓冲存储器信息传输
公开(公告)号：US5623700A
公开(公告)日：1997-04-22
申请号：US223874
申请日：1994-04-06
申请人： Terry J. Parks , Craig S. Jones , Darius D. Gaskins
发明人： Terry J. Parks , Craig S. Jones , Darius D. Gaskins
IPC分类号： G06F12/08 , G06F13/38 , G06F13/14
CPC分类号： G06F12/0835 , G06F12/0866 , G06F13/385
摘要： A caching disk controller is provided which includes a bus bridge that forms an interface between a memory of the disk controller and a host computer. The caching disk controller further includes a SCSI processor for controlling the transfer of data from a SCSI disk drive to the memory via a local bus. A zero latency DMA controller embodied within the bus bridge snoops the local bus as data is being transferred from the SCSI disk drive to the memory, and thereby allows the data to be sequentially latched within a data FIFO of the bus bridge concurrently with its transfer into the memory. As a result, the requested data may be advantageously provided from the bus bridge to the host computer with reduced delay, while the data continues to be stored within the memory to accommodate high hit rates during subsequent transfers.
摘要翻译：提供了一种缓存磁盘控制器，其包括形成磁盘控制器的存储器和主计算机之间的接口的总线桥。缓存磁盘控制器还包括SCSI处理器，用于经由本地总线控制从SCSI磁盘驱动器传送到存储器的数据。当数据正在从SCSI磁盘驱动器传输到存储器时，总线桥中实现的零延迟DMA控制器会窥探本地总线，从而允许数据在总线桥的数据FIFO中顺序锁存，同时传输到记忆。结果，可以有利地从所述总线桥提供所请求的数据到具有减小的延迟的主计算机，同时数据继续存储在存储器内以在后续传送期间适应高命中率。

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