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1. 发明授权

US07057965B2 Method of performing access to a single-port memory device, memory access device, integrated circuit device and method of use of an integrated circuit device 失效
标题翻译：访问单端口存储器件，存储器存取器件，集成电路器件以及使用集成电路器件的方法的方法
公开(公告)号：US07057965B2
公开(公告)日：2006-06-06
申请号：US10512031
申请日：2003-04-14
申请人： Corneliu Tobescu , Antonius Petrus Gerardus Welbers
发明人： Corneliu Tobescu , Antonius Petrus Gerardus Welbers
IPC分类号： C11C8/00
CPC分类号： G11C7/22 , G11C7/1075
摘要： An arbiter 15 for accessing a single-port RAM 13 without the need to use a hand-shaking protocol is proposed. This allows simultaneous read and write accesses to a single-port RAM 13. All write accesses are delayed so that the arbiter 15 can detect if there is a simultaneous read access. If there is a read access, the read access is delayed until the write access is completed.
摘要翻译：提出了一种用于访问单端口RAM13而不需要使用移动协议的仲裁器15。这允许对单端口RAM 13的同时读和写访问。所有的写访问被延迟，使得仲裁器15可以检测是否存在同时的读访问。如果存在读取访问权限，则读取访问被延迟，直到写入访问完成。

2. 发明申请

US20050180254A1 Method of performing access to a single-port memory device, memory access device, integrated circuit device and method of use of an integrated circuit device 失效
标题翻译：访问单端口存储器件，存储器存取器件，集成电路器件以及使用集成电路器件的方法的方法
公开(公告)号：US20050180254A1
公开(公告)日：2005-08-18
申请号：US10512031
申请日：2003-04-14
申请人： Corneliu Tobescu , Antonius Petrus Welbers
发明人： Corneliu Tobescu , Antonius Petrus Welbers
IPC分类号： G11C11/41 , G06F12/00 , G06F12/06 , G11C7/10 , G11C7/22 , G11C8/00
CPC分类号： G11C7/22 , G11C7/1075
摘要： An arbiter 15 for accessing a single-port RAM 13 without the need to use a hand-shaking protocol is proposed. This allows simultaneous read and write accesses to a single-port RAM 13. All write accesses are delayed so that the arbiter 15 can detect if there is a simultaneous read access. If there is a read access, the read access is delayed until the write access is completed.
摘要翻译：提出了一种用于访问单端口RAM13而不需要使用移动协议的仲裁器15。这允许对单端口RAM 13的同时读和写访问。所有的写访问被延迟，使得仲裁器15可以检测是否存在同时的读访问。如果存在读取访问权限，则读取访问被延迟，直到写入访问完成。

3. 发明申请

US20070273635A1 Circuit Arrangement for Driving Arrangement 审中-公开
标题翻译：行车安排电路安排
公开(公告)号：US20070273635A1
公开(公告)日：2007-11-29
申请号：US10579638
申请日：2004-11-10
申请人： Antonius Welbers , Corneliu Tobescu , Francesco Maone
发明人： Antonius Welbers , Corneliu Tobescu , Francesco Maone
IPC分类号： G09G3/36
CPC分类号： G09G3/3688 , G09G2310/0275 , G09G2310/0297
摘要： The invention concerns a circuit arrangement (2) for driving a display arrangement (1). Further it concerns a display arrangement (1) and a method for driving a display arrangement (1). To provide an arrangement (2) having a good offset cancellation combined with high quality illustrating of an image the circuit arrangement includes column driving means (5) for driving n column electrodes (C) and row driving means (4) for driving m row electrodes (R) of the display arrangement (1), wherein the column driving means (5) comprises n output channels (O), each output channel (O) having a column electrode (C) assigned and is arranged for providing a respective column voltage to the assigned column electrode (C), an additional output channel (OR) is arranged for providing a respective column voltage, whereas each of the n column electrodes (C) is connectable to the additional output channel (OR). The additional output channel (OR) will be calibrated at first. Then the additional output channel will successively replace the output channel (O1-On) whereas during replacement the output channels (O1-On) will be calibrated sequentially. So the time required for offset cancellation will not reduce the time for settling the column voltage.
摘要翻译：本发明涉及用于驱动显示装置（1）的电路装置（2）。此外，它涉及显示装置（1）和用于驱动显示装置（1）的方法。为了提供具有良好的偏移消除的结构（2）和高质量的图像的图像，电路装置包括用于驱动n列电极（C）的列驱动装置（5）和用于驱动m行电极的行驱动装置（4）（1）的显示装置（R），其中列驱动装置（5）包括n个输出通道（O），每个输出通道（O）具有分配的列电极（C），并且被布置用于提供相应的列电压配置到分配的列电极（C），设置附加的输出通道（O SUB R）以提供相应的列电压，而n列电极（C）中的每一个可连接到附加的输出通道（O R R）。首先校准附加的输出通道（O SUB R＆）。然后附加的输出通道将相继地替换输出通道（O SUB 1 -O SUB SUB），而在更换期间输出通道（O SUB 1 -O ）将被顺序校准。因此，偏移消除所需的时间不会减少设置列电压的时间。

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