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1. 发明申请

US20130085703A1 Histogram-Based Linearization of Analog-to-Digital Converters 审中-公开
标题翻译：模数转换器的基于直方图的线性化
公开(公告)号：US20130085703A1
公开(公告)日：2013-04-04
申请号：US13249845
申请日：2011-09-30
申请人： Ray (Ramon) GOMEZ , Bruce J. Currivan , Lin He , Loke Tan , Frank Van der Goes , Cy (Chun-Ying) Chen , Jiangfeng Wu , Thomas Kolze
发明人： Ray (Ramon) GOMEZ , Bruce J. Currivan , Lin He , Loke Tan , Frank Van der Goes , Cy (Chun-Ying) Chen , Jiangfeng Wu , Thomas Kolze
IPC分类号： G06F17/17 , G06F19/00
CPC分类号： G06F17/17 , H03M1/1042 , H03M1/12
摘要： Embodiments provide histogram-based methods and system to estimate the transfer function of an ADC, and subsequently to linearize a non-linear ADC transfer function. Embodiments include blind algorithms that require no a priori knowledge of the input signal distribution. Embodiments can be implemented using cumulative (i.e., cumulative distribution function (CDF)) or non-cumulative (i.e., probability density function (PDF)) histograms. According to embodiments, a non-linear transfer function can be estimated by linearly approximating successive local intervals of the transfer function. Linearly approximated successive local intervals of the transfer function can then be used to fully characterize and closely estimate the transfer function.
摘要翻译：实施例提供基于直方图的方法和系统来估计ADC的传递函数，并且随后对非线性ADC传递函数进行线性化。实施例包括不需要输入信号分布的先验知识的盲算法。实施例可以使用累积（即，累积分布函数（CDF））或非累积（即，概率密度函数（PDF））直方图来实现。根据实施例，可以通过线性近似传递函数的连续局部间隔来估计非线性传递函数。传递函数的线性逼近的连续局部间隔可用于完全表征和密切估计传递函数。

2. 发明授权

US08181045B2 Power control bus 有权
标题翻译：电源控制总线
公开(公告)号：US08181045B2
公开(公告)日：2012-05-15
申请号：US12724204
申请日：2010-03-15
申请人： Neil Y. Kim , Pieter Vorenkamp , Sumant Ranganathan , Chun-ying Chen
发明人： Neil Y. Kim , Pieter Vorenkamp , Sumant Ranganathan , Chun-ying Chen
IPC分类号： G06F1/00
CPC分类号： G06F1/266
摘要： A circuit and method utilizing a power control data bus for implementing power control. Various aspects of the present invention provide an electrical circuit that comprises a power supply circuit that outputs electrical power. The electrical circuit may also comprise an integrated circuit that receives electrical power from the power supply circuit. The electrical circuit may also comprise a power control data bus, which communicatively couples a power control data bus interface of the power supply circuit and a power control data bus interface of the integrated circuit. The power control data bus may, for example, carry power control data between the integrated circuit and the power supply circuit. Various aspects of the present invention also provide a method that comprises communicating power control data over a power control data bus and utilizing the power control data to control characteristics of electrical power provided to an integrated circuit or module.
摘要翻译：一种利用功率控制数据总线实现功率控制的电路和方法。本发明的各个方面提供一种电路，其包括输出电力的电源电路。电路还可以包括从电源电路接收电力的集成电路。电路还可以包括功率控制数据总线，其通信地耦合电源电路的功率控制数据总线接口和集成电路的功率控制数据总线接口。功率控制数据总线可以例如在集成电路和电源电路之间承载功率控制数据。本发明的各个方面还提供了一种方法，其包括在功率控制数据总线上通信功率控制数据，并利用功率控制数据来控制提供给集成电路或模块的电力的特性。

3. 发明授权

US08179293B2 Programmable settling for high speed analog to digital converter 有权
标题翻译：可编程稳定的高速模数转换器
公开(公告)号：US08179293B2
公开(公告)日：2012-05-15
申请号：US12954024
申请日：2010-11-24
申请人： Chun-Ying Chen
发明人： Chun-Ying Chen
IPC分类号： H03M1/12
CPC分类号： H03M1/1014
摘要： In an embodiment, an apparatus and method reduces a calibration settling time in an analog-to-digital converter (ADC). The ADC has a reference voltage supply. The reference voltage supply has an output. A filter capacitor is coupled to the reference voltage supply output. An isolation transistor is series-coupled between the filter capacitor and ground. The isolation transistor isolates the filter capacitor during calibration of the ADC.
摘要翻译：在一个实施例中，装置和方法降低了模数转换器（ADC）中的校准建立时间。 ADC具有参考电压供应。参考电压源有一个输出。滤波电容器耦合到参考电压电源输出。隔离晶体管串联耦合在滤波电容和地之间。隔离晶体管在ADC校准期间隔离滤波电容。

4. 发明授权

US08072096B2 Integrated circuit with multiple independent power supply zones 有权
标题翻译：具有多个独立电源区的集成电路
公开(公告)号：US08072096B2
公开(公告)日：2011-12-06
申请号：US12829980
申请日：2010-07-02
申请人： Sumant Ranganathan , Pieter Vorenkamp , Neil Y. Kim , Chun-ying Chen
发明人： Sumant Ranganathan , Pieter Vorenkamp , Neil Y. Kim , Chun-ying Chen
IPC分类号： H02J1/10
CPC分类号： H05K1/0262 , H05K1/181 , Y10T307/50
摘要： An integrated circuit comprising multiple independent power supply zones at substantially the same voltage level and a method for utilizing such power supply zones. An integrated circuit may comprise a first module and may, for example, comprise a second module. A first power supply bus may communicate first electrical power to the first module, where the first electrical power is characterized by a first set of power characteristics comprising a first voltage level. A second power supply bus may communicate second power to the second module, where the second power is characterized by a second set of power characteristics comprising a second voltage level that is substantially similar to the first voltage level. The second set of power characteristics may, for example, be substantially different than the first set of power characteristics. The second power supply bus may also, for example, communicate the second electrical power to the first module.
摘要翻译：一种集成电路，包括在基本上相同的电压电平下的多个独立电源区域以及用于利用这种电源区域的方法。集成电路可以包括第一模块，并且可以例如包括第二模块。第一电源总线可以将第一电力传送到第一模块，其中第一电功率由包括第一电压电平的第一组功率特性表征。第二电源总线可以向第二模块通信第二功率，其中第二功率由包括基本上类似于第一电压电平的第二电压电平的第二组功率特性表征。第二组功率特性可以例如与第一组功率特性基本上不同。第二电源总线也可以例如将第二电力传送到第一模块。

5. 发明申请

US20110032131A1 Analog To Digital Converter with Dynamic Power Configuration 有权
标题翻译：具有动态功率配置的模数转换器
公开(公告)号：US20110032131A1
公开(公告)日：2011-02-10
申请号：US12906772
申请日：2010-10-18
申请人： Chun-Ying CHEN
发明人： Chun-Ying CHEN
IPC分类号： H03M1/00 , H03M1/12
CPC分类号： H03M1/002
摘要： In an embodiment, an analog to digital converter (ADC) has a dynamic power circuit. The ADC has a track-and-hold circuit with an output and a track mode. The ADC also has a comparator with an input. A preamplifier is coupled between the track-and-hold output and the comparator input. At least one of a preamplifier current and a comparator current are limited during the track mode to reduce ADC power consumption.
摘要翻译：在一个实施例中，模数转换器（ADC）具有动态功率电路。 ADC具有跟踪和保持电路，具有输出和跟踪模式。 ADC还具有一个带有输入的比较器。前置放大器耦合在跟踪保持输出和比较器输入之间。在跟踪模式期间，前置放大器电流和比较器电流中的至少一个受到限制，以降低ADC功耗。

6. 发明授权

US07751516B2 Inter-device adaptable interfacing clock skewing 有权
标题翻译：设备间适配性接口时钟偏移
公开(公告)号：US07751516B2
公开(公告)日：2010-07-06
申请号：US11358148
申请日：2006-02-21
申请人： Andrew J. Castellano , Pieter Vorenkamp , Chun-Ying Chen
发明人： Andrew J. Castellano , Pieter Vorenkamp , Chun-Ying Chen
IPC分类号： H04L7/00
CPC分类号： H04L7/0008 , H04L7/0037
摘要： Inter-device adaptable interfacing clock skewing. The invention is operable in either one of both of a transmit mode and a receive mode to perform skewing of a transmitted and/or a received signal. The operational parameters including frequency and phase may be determined during auto detect/auto negotiation, they may be programmed externally, or they may be user selected in various embodiments. A device may include a clock generator, one or more divider, and one or more delay cells internally to the device. If desired, a high frequency clock is generated within the device and then divided down to generate the appropriate clock signal that supports the communication and interaction between multiple devices. Registers and/or pins may be used to select the clock frequency and phase of output clock signals. The present invention supports multiple Ethernet protocols between multiple devices including 10BaseT, 100BaseT, and 1000BaseT.
摘要翻译：设备间适配性接口时钟偏移。本发明可以在发射模式和接收模式两者中的任一个中操作，以执行发送和/或接收信号的偏移。可以在自动检测/自动协商期间确定包括频率和相位的操作参数，它们可以在外部编程，或者可以在各种实施例中用户选择。设备可以在设备内部包括时钟发生器，一个或多个分频器以及一个或多个延迟单元。如果需要，在器件内产生高频时钟，然后分频，以产生支持多个器件之间通信和交互的适当时钟信号。寄存器和/或引脚可用于选择时钟频率和输出时钟信号的相位。本发明支持多个设备之间的多个以太网协议，包括10BaseT，100BaseT和1000BaseT。

7. 发明授权

US07707434B2 Power control bus for carrying power control information indicating a power supply voltage variability 有权
标题翻译：功率控制总线，用于承载指示电源电压变化的功率控制信息
公开(公告)号：US07707434B2
公开(公告)日：2010-04-27
申请号：US11166631
申请日：2005-06-24
申请人： Neil Y. Kim , Pieter Vorenkamp , Sumant Ranganathan , Chun-ying Chen
发明人： Neil Y. Kim , Pieter Vorenkamp , Sumant Ranganathan , Chun-ying Chen
IPC分类号： G06F1/00
CPC分类号： G06F1/266
摘要： A circuit and method utilizing a power control data bus for implementing power control. Various aspects of the present invention provide an electrical circuit that comprises a power supply circuit that outputs electrical power. The electrical circuit may also comprise an integrated circuit that receives electrical power from the power supply circuit. The electrical circuit may also comprise a power control data bus, which communicatively couples a power control data bus interface of the power supply circuit and a power control data bus interface of the integrated circuit. The power control data bus may, for example, carry power control data between the integrated circuit and the power supply circuit. Various aspects of the present invention also provide a method that comprises communicating power control data over a power control data bus and utilizing the power control data to control characteristics of electrical power provided to an integrated circuit or module.
摘要翻译：一种利用功率控制数据总线实现功率控制的电路和方法。本发明的各个方面提供一种电路，其包括输出电力的电源电路。电路还可以包括从电源电路接收电力的集成电路。电路还可以包括功率控制数据总线，其通信地耦合电源电路的功率控制数据总线接口和集成电路的功率控制数据总线接口。功率控制数据总线可以例如在集成电路和电源电路之间承载功率控制数据。本发明的各个方面还提供了一种方法，其包括在功率控制数据总线上通信功率控制数据，并利用功率控制数据来控制提供给集成电路或模块的电力的特性。

8. 发明授权

US07705463B2 Biasing device for low parasitic capacitance in integrated circuit applications 有权
标题翻译：用于集成电路应用中的低寄生电容的偏置装置
公开(公告)号：US07705463B2
公开(公告)日：2010-04-27
申请号：US11473043
申请日：2006-06-23
申请人： Chun-Ying Chen
发明人： Chun-Ying Chen
IPC分类号： H01L23/52
CPC分类号： H01L29/92 , H01L29/94
摘要： The present invention is directed to an apparatus and method for reducing a parasitic capacitance in an integrated circuit. The apparatus includes a substrate and a biasing device. The substrate has a circuit disposed thereon, wherein a first capacitance exists between the substrate and an element of the circuit. The biasing device DC biases a first portion of the substrate to a voltage different than a voltage of a second portion of the substrate, thereby inducing a second capacitance between the first portion of the substrate and the second portion of the substrate. The second capacitance is in series with the first capacitance.
摘要翻译：本发明涉及用于减小集成电路中的寄生电容的装置和方法。该装置包括基板和偏置装置。衬底具有设置在其上的电路，其中在衬底和电路的元件之间存在第一电容。偏置器件DC将衬底的第一部分偏置到不同于衬底的第二部分的电压的电压，从而在衬底的第一部分和衬底的第二部分之间引起第二电容。第二电容与第一电容串联。

9. 发明申请

US20090058699A1 Programmable settling for high speed analog to digital converter 有权
标题翻译：可编程稳定的高速模数转换器
公开(公告)号：US20090058699A1
公开(公告)日：2009-03-05
申请号：US12289460
申请日：2008-10-28
申请人： Chun-Ying Chen
发明人： Chun-Ying Chen
IPC分类号： H03M1/10
CPC分类号： H03M1/1014
摘要： In an embodiment, an apparatus and method reduces a calibration settling time in an analog-to-digital converter (ADC). The ADC has a reference voltage supply. The reference voltage supply has an output. A filter capacitor is coupled to the reference voltage supply output. An isolation transistor is series-coupled between the filter capacitor and ground. The isolation transistor isolates the filter capacitor during calibration of the ADC.
摘要翻译：在一个实施例中，装置和方法降低了模数转换器（ADC）中的校准建立时间。 ADC具有参考电压供应。参考电压源有一个输出。滤波电容器耦合到参考电压电源输出。隔离晶体管串联耦合在滤波电容和地之间。隔离晶体管在ADC校准期间隔离滤波电容。

10. 发明申请

US20070120591A1 Regulated charge pump with digital resistance control 失效
标题翻译：具有数字电阻控制的调节电荷泵
公开(公告)号：US20070120591A1
公开(公告)日：2007-05-31
申请号：US11585841
申请日：2006-10-25
申请人： Yee Cheung , Chun-Ying Chen
发明人： Yee Cheung , Chun-Ying Chen
IPC分类号： G05F1/10
CPC分类号： H02M3/073 , H02M2001/0041
摘要： A charge pump includes a resistor divider connected between an output voltage node and ground and a comparator inputting a reference voltage at one input, and a divided voltage from the resistor divider at another input. A digital control circuit is enabled by the comparator. A first transistor and a second transistor are in series between an input voltage node and the ground, both transistors controlled by the digital control circuit. A pump capacitor is connected between to the output voltage node and between the first and second transistor, and being charged by turning the first and second transistors on and off. A first diode is between the pump capacitor and the input voltage node. A second diode between the pump capacitor and the output voltage node. A reservoir capacitor between the output voltage node and ground. The digital control circuit comprises a first shift register. The first transistor comprises a first plurality of parallel transistors, the first shift register includes any of a first plurality of DQ, RS or JK flip flops connected in series, and outputs of the flip flops control gates of the first plurality of parallel transistors.
摘要翻译：电荷泵包括连接在输出电压节点和地之间的电阻分压器和在一个输入端输入参考电压的比较器，以及在另一个输入端分别来自电阻分压器的分压电压。数字控制电路由比较器使能。第一晶体管和第二晶体管串联在输入电压节点和地之间，两个晶体管都由数字控制电路控制。泵浦电容器连接到输出电压节点之间，并且连接在第一和第二晶体管之间，并通过使第一和第二晶体管导通和关断而被充电。第一个二极管位于泵电容器和输入电压节点之间。泵电容器和输出电压节点之间的第二个二极管。输出电压节点与地之间的储层电容。数字控制电路包括第一移位寄存器。第一晶体管包括第一多个并联晶体管，第一移位寄存器包括串联连接的第一多个DQ，RS或JK触发器中的任一个以及第一多个并联晶体管的触发器控制栅极的输出。

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