专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20120070915A1 METHOD FOR COPPER HILLOCK REDUCTION 有权
标题翻译：铜减少方法
公开(公告)号：US20120070915A1
公开(公告)日：2012-03-22
申请号：US12938158
申请日：2010-11-02
申请人： DUO HUI BEI , MING YUAN LIU , CHUN SHENG ZHENG
发明人： DUO HUI BEI , MING YUAN LIU , CHUN SHENG ZHENG
IPC分类号： H01L21/66
CPC分类号： H01L21/76877 , H01L21/02167 , H01L21/02299 , H01L21/76883
摘要： A method of forming interconnects in integrated circuits includes providing a semiconductor substrate and forming a copper interconnect structure that is formed overlying a barrier layer within a thickness of an interlayer dielectric layer. The copper interconnect structure has a first stress characteristic. The method further loads the semiconductor substrate including the copper interconnect structure into a deposition chamber that contains an inert environment. The semiconductor substrate including the copper interconnect structure is annealed in the inert environment for a period of time to cause the copper interconnect structure to have a second stress characteristic. The semiconductor substrate is maintained in the deposition chamber while an etch stop layer is deposited thereon. The method further deposits an inner-metal dielectric layer overlying the etch stop layer, wherein the annealing reduces copper hillock defects resulting from at least the first stress characteristic.
摘要翻译：在集成电路中形成互连的方法包括提供半导体衬底并形成覆盖在层间电介质层的厚度内的阻挡层的铜互连结构。铜互连结构具有第一应力特性。该方法还将包括铜互连结构的半导体衬底加载到包含惰性环境的沉积室中。包括铜互连结构的半导体衬底在惰性环境中退火一段时间，以使铜互连结构具有第二应力特性。将半导体衬底保持在沉积室中，同时沉积蚀刻停止层。该方法还沉积覆盖在蚀刻停止层上的内金属介电层，其中退火减少了由至少第一应力特性导致的铜小丘缺陷。

2. 发明授权

US08815615B2 Method for copper hillock reduction 有权
标题翻译：铜小丘降低的方法
公开(公告)号：US08815615B2
公开(公告)日：2014-08-26
申请号：US12938158
申请日：2010-11-02
申请人： Duo Hui Bei , Ming Yuan Liu , Chun Sheng Zheng
发明人： Duo Hui Bei , Ming Yuan Liu , Chun Sheng Zheng
IPC分类号： G01R31/26
CPC分类号： H01L21/76877 , H01L21/02167 , H01L21/02299 , H01L21/76883
摘要： A method of forming interconnects in integrated circuits includes providing a semiconductor substrate and forming a copper interconnect structure that is formed overlying a barrier layer within a thickness of an interlayer dielectric layer. The copper interconnect structure has a first stress characteristic. The method further loads the semiconductor substrate including the copper interconnect structure into a deposition chamber that contains an inert environment. The semiconductor substrate including the copper interconnect structure is annealed in the inert environment for a period of time to cause the copper interconnect structure to have a second stress characteristic. The semiconductor substrate is maintained in the deposition chamber while an etch stop layer is deposited thereon. The method further deposits an intermetal dielectric layer overlying the etch stop layer, wherein the annealing reduces copper hillock defects resulting from at least the first stress characteristic.
摘要翻译：在集成电路中形成互连的方法包括提供半导体衬底并形成覆盖在层间电介质层的厚度内的阻挡层的铜互连结构。铜互连结构具有第一应力特性。该方法还将包括铜互连结构的半导体衬底加载到包含惰性环境的沉积室中。包括铜互连结构的半导体衬底在惰性环境中退火一段时间，以使铜互连结构具有第二应力特性。将半导体衬底保持在沉积室中，同时沉积蚀刻停止层。该方法还沉积覆盖在蚀刻停止层上的金属间电介质层，其中退火减少了由至少第一应力特性导致的铜小丘缺陷。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式