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1. 发明授权

US5875007A Motion image (MPEG II) video stream multiplexing system 失效
标题翻译：运动图像（MPEG II）视频流复用系统
公开(公告)号：US5875007A
公开(公告)日：1999-02-23
申请号：US758152
申请日：1996-11-25
申请人： Chul Hyung Zhung , Hyo Joong Kim , Sung Soo Kang
发明人： Chul Hyung Zhung , Hyo Joong Kim , Sung Soo Kang
IPC分类号： H04N7/52 , H04N7/56 , H04N21/236 , H04N21/242 , H04N21/434 , H04N7/22
CPC分类号： H04N21/23608 , H04N21/242 , H04N21/4344 , H04N7/52 , H04N7/56
摘要： A motion image( MPEG II) video stream transmission system for transferring MPEG II video stream to a subscriber by receiving 6 channels of a motion image(MPEG II) video stream, and includes: a MPEG II encoder for encoding an analog video signal on a motion image video signal; a framer for framing and outputting a MPEG II video stream by controlling a read clock of pure data of the MPEG II video stream whenever data is variable, registering a transmission velocity information to a video stream inputted in the MPEG II encoder; a first multiplexing means; a second-stage multiplexer; a headend having an optical transmission means; an optical transmission system; a first-stage demultiplexing means; a second-stage demultiplexing means; a remote terminal having a video switching system; and a subscriber terminal apparatus for converting the MPEG II video signal into an analog signal after reframing a video signal outputted from the remote terminal and outputting the converted signal.
摘要翻译：一种运动图像（MPEG II）视频流传输系统，用于通过接收6个运动图像（MPEG II）视频流来传送MPEG II视频流到用户，并且包括：MPEG II编码器，用于对模拟视频信号进行编码运动图像视频信号; 一个成帧器，用于通过每当数据可变时控制MPEG II视频流的纯数据的读取时钟来对MPEG II视频流进行成帧和输出，将传输速度信息注册到MPEG II编码器中输入的视频流中; 第一复用装置; 第二级多路复用器; 具有光传输装置的前端; 光传输系统; 第一级解复用装置; 第二级解复用装置; 具有视频切换系统的远程终端; 以及用户终端装置，用于在重构从远程终端输出的视频信号之后将MPEG II视频信号转换为模拟信号，并输出转换的信号。

2. 发明申请

US20070133560A1 Method and apparatus for processing packet in high speed router 失效
标题翻译：高速路由器处理数据包的方法和装置
公开(公告)号：US20070133560A1
公开(公告)日：2007-06-14
申请号：US11634730
申请日：2006-12-06
申请人： Kook Nam , Hak-Suh Kim , Jae Young , Chul Hyung , Bup Joong , Byung Ahn
发明人： Kook Nam , Hak-Suh Kim , Jae Young , Chul Hyung , Bup Joong , Byung Ahn
IPC分类号： H04L12/56 , H04L12/28
CPC分类号： H04L45/00 , H04L45/52 , H04L45/54 , H04L45/60 , H04L45/745 , H04L49/3009
摘要： An apparatus for processing packets in a high speed router and a method thereof are provided. The high speed router includes a forward processor and a control processor where the forward processor having an input terminal processor and an output terminal processor. The output terminal processor manages a Layer 2 Address Table by dividing the Layer 2 Address Table into a layer 2 indirect address table and a layer 2 direct address table and by managing them. The indirect address table is directly indexed in the Next-hop Table of the input terminal processor table. The direct address table is composed of a hashing table for a destination IP address. Therefore, the system efficiency can be improved by reducing the memory which is used for storing the forwarding information table occupied by the forward processor and by reducing the IPC message between the control processor and the forwarding process.
摘要翻译：提供了一种用于处理高速路由器中的分组的装置及其方法。高速路由器包括前向处理器和控制处理器，其中前向处理器具有输入端处理器和输出端处理器。输出终端处理器通过将第2层地址表划分为第2层间接地址表和第2层直接地址表并对其进行管理来管理二层地址表。间接地址表直接索引在输入终端处理器表的下一跳表中。直接地址表由目的IP地址的散列表组成。因此，可以通过减少用于存储前向处理器所占用的转发信息表的存储器以及通过减少控制处理器与转发过程之间的IPC消息来提高系统效率。

3. 发明授权

US07729362B2 Method and apparatus for processing packet in high speed router 失效
标题翻译：高速路由器处理数据包的方法和装置
公开(公告)号：US07729362B2
公开(公告)日：2010-06-01
申请号：US11634730
申请日：2006-12-06
申请人： Kook Jin Nam , Hak Suh Kim , Jae Young Kim , Chul Hyung Zhung , Bup Joong Kim , Byung Jun Ahn
发明人： Kook Jin Nam , Hak Suh Kim , Jae Young Kim , Chul Hyung Zhung , Bup Joong Kim , Byung Jun Ahn
IPC分类号： H04L12/28
CPC分类号： H04L45/00 , H04L45/52 , H04L45/54 , H04L45/60 , H04L45/745 , H04L49/3009
摘要： An apparatus for processing packets in a high speed router and a method thereof are provided. The high speed router includes a forward processor and a control processor where the forward processor having an input terminal processor and an output terminal processor. The output terminal processor manages a Layer 2 Address Table by dividing the Layer 2 Address Table into a layer 2 indirect address table and a layer 2 direct address table and by managing them. The indirect address table is directly indexed in the Next-hop Table of the input terminal processor table. The direct address table is composed of a hashing table for a destination IP address. Therefore, the system efficiency can be improved by reducing the memory which is used for storing the forwarding information table occupied by the forward processor and by reducing the IPC message between the control processor and the forwarding process.
摘要翻译：提供了一种用于处理高速路由器中的分组的装置及其方法。高速路由器包括前向处理器和控制处理器，其中前向处理器具有输入端处理器和输出端处理器。输出终端处理器通过将第2层地址表划分为第2层间接地址表和第2层直接地址表并对其进行管理来管理二层地址表。间接地址表直接索引在输入终端处理器表的下一跳表中。直接地址表由目的IP地址的散列表组成。因此，可以通过减少用于存储前向处理器所占用的转发信息表的存储器以及通过减少控制处理器与转发过程之间的IPC消息来提高系统效率。

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