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1. 发明授权

US09489208B2 Operating a pipeline flattener in order to track instructions for complex breakpoints 有权
标题翻译：操作管道压平机，以便跟踪复杂断点的指令
公开(公告)号：US09489208B2
公开(公告)日：2016-11-08
申请号：US13473260
申请日：2012-05-16
申请人： Markus Koesler , Johann Zipperer , Christian Wiencke , Wolfgang Lutsch
发明人： Markus Koesler , Johann Zipperer , Christian Wiencke , Wolfgang Lutsch
IPC分类号： G06F11/36 , G06F9/38 , G06F11/267
CPC分类号： G06F9/3867 , G06F9/30098 , G06F9/3802 , G06F9/3869 , G06F11/267 , G06F11/3636 , G06F11/3648
摘要： A semiconductor device comprising a processor having a pipelined architecture and a pipeline flattener and a method for operating a pipeline flattener in a semiconductor device are provided. The processor comprises a pipeline having a plurality of pipeline stages and a plurality of pipeline registers that are coupled between the pipeline stages. The pipeline flattener comprises a plurality of trigger registers for storing a trigger, wherein the trigger registers are coupled between the pipeline stages.
摘要翻译：提供一种半导体器件，其包括具有流水线结构的处理器和管道平整器以及用于在半导体器件中操作管道平整器的方法。处理器包括具有多个流水线级的流水线和耦合在流水线级之间的多个流水线寄存器。管道压扁机包括多个用于存储触发器的触发寄存器，其中触发寄存器耦合在流水线级之间。

2. 发明授权

US09047140B2 Independently timed multiplier 有权
标题翻译：独立定时乘数
公开(公告)号：US09047140B2
公开(公告)日：2015-06-02
申请号：US13559832
申请日：2012-07-27
申请人： Christian Wiencke , Horst Diewald
发明人： Christian Wiencke , Horst Diewald
IPC分类号： G06F7/523 , G06F7/53
CPC分类号： G06F7/5312
摘要： An independently timed multiplier unit includes a multiplier and a clock generator. The multiplier has a first set of semiconductor circuits in a critical path. The clock generator has a second set of semiconductor circuits configured to control a clock period of said clock generator selected to set a clock period longer than the propagation delay through the critical path of the multiplier. The clock generator may include a delay circuit having a delay to set the clock period longer than the propagation delay through the critical path of said multiplier. The clock generator uses circuit with identical logical design including the same standard cells, the same logic design or the same floor plan. Close matching of these circuit causes the multiplier and the clock generator to experience the same PVT speed variations.
摘要翻译：独立定时乘法器单元包括乘法器和时钟发生器。乘法器在关键路径中具有第一组半导体电路。时钟发生器具有第二组半导体电路，其被配置为控制所选择的所述时钟发生器的时钟周期，以设置比通过乘法器的关键路径的传播延迟更长的时钟周期。时钟发生器可以包括具有延迟的延迟电路，以将时钟周期设置为比通过所述乘法器的关键路径的传播延迟更长。时钟发生器使用具有相同逻辑设计的电路，包括相同的标准单元，相同的逻辑设计或相同的平面图。这些电路的紧密匹配使乘法器和时钟发生器经历相同的PVT速度变化。

3. 发明申请

US20130046962A1 Operating a Pipeline Flattener in a Semiconductor Device 有权
标题翻译：在半导体器件中操作管道闪络器
公开(公告)号：US20130046962A1
公开(公告)日：2013-02-21
申请号：US13473260
申请日：2012-05-16
申请人： Markus Koesler , Johann Zipperer , Christian Wiencke , Wolfgang Lutsch
发明人： Markus Koesler , Johann Zipperer , Christian Wiencke , Wolfgang Lutsch
IPC分类号： G06F11/30 , G06F9/30
CPC分类号： G06F9/3867 , G06F9/30098 , G06F9/3802 , G06F9/3869 , G06F11/267 , G06F11/3636 , G06F11/3648
摘要： A semiconductor device comprising a processor having a pipelined architecture and a pipeline flattener and a method for operating a pipeline flattener in a semiconductor device are provided. The processor comprises a pipeline having a plurality of pipeline stages and a plurality of pipeline registers that are coupled between the pipeline stages. The pipeline flattener comprises a plurality of trigger registers for storing a trigger, wherein the trigger registers are coupled between the pipeline stages.
摘要翻译：提供一种半导体器件，其包括具有流水线结构的处理器和管道平整器以及用于在半导体器件中操作管道平整器的方法。处理器包括具有多个流水线级的流水线和耦合在流水线级之间的多个流水线寄存器。管道压扁机包括多个用于存储触发器的触发寄存器，其中触发寄存器耦合在流水线级之间。

4. 发明授权

US07561541B2 Deep sleep mode for WLAN communication systems 有权
标题翻译： WLAN通信系统的深度睡眠模式
公开(公告)号：US07561541B2
公开(公告)日：2009-07-14
申请号：US10925112
申请日：2004-08-24
申请人： Tilo Ferchland , Ralf Flemming , Christian Wiencke
发明人： Tilo Ferchland , Ralf Flemming , Christian Wiencke
IPC分类号： G08C17/00
CPC分类号： H04W52/0287 , H04W84/12 , Y02D70/142
摘要： A WLAN (Wireless Local Area Network) communication device for performing communication in a WLAN network is provided that comprises a physical connection unit, a physical connection oscillator, and a control unit. The physical connection unit is for providing a physical connection of the WLAN communication device to a wireless communication medium. The physical connection oscillator is for providing a physical connection clock signal to the physical connection unit. The control unit is for controlling operation of the physical connection oscillator. The WLAN communication device is operable in a communication mode and in a deep sleep mode. The control unit is adapted to deactivate the physical connection oscillator when the deep sleep mode is entered. Embodiments may provide an extended reduction of the power consumption of the WLAN communication device.
摘要翻译：提供了一种用于在WLAN网络中执行通信的WLAN（无线局域网）通信设备，其包括物理连接单元，物理连接振荡器和控制单元。物理连接单元用于提供WLAN通信设备到无线通信介质的物理连接。物理连接振荡器用于向物理连接单元提供物理连接时钟信号。控制单元用于控制物理连接振荡器的操作。 WLAN通信设备可以在通信模式和深度睡眠模式下操作。控制单元适于在进入深度睡眠模式时停用物理连接振荡器。实施例可以提供WLAN通信设备的功耗的扩展减少。

5. 发明申请

US20080243976A1 MULTIPLY AND MULTIPLY AND ACCUMULATE UNIT 审中-公开
标题翻译：多重和累积单元
公开(公告)号：US20080243976A1
公开(公告)日：2008-10-02
申请号：US12057625
申请日：2008-03-28
申请人： Christian Wiencke
发明人： Christian Wiencke
IPC分类号： G06F7/523 , G06F7/57
CPC分类号： G06F7/5312 , G06F7/5324 , G06F7/5443 , G06F2207/3812 , G06F2207/382
摘要： The present invention relates to a multiply apparatus and a method for multiplying a first operand consisting of na bits and a second operand consisting of nx bits. In one embodiment the multiply apparatus comprising a CSA (CSA) unit with nx rows each comprising na AND gates for calculating a single bit product of two single bit input values and adder cells for adding results of a preceding row to a following row and a last output row for outputting a carry vector and a sum vector, and logic circuitry for selectively inverting the single bit products at the most significant position of the nx−1 first rows and at the na−1 least significant positions of the output row in response to a first configuration signal before inputting the selectively inverted single bit products to respective adder cells for switching the CSA unit selectively between processing of signed two's complement operands and unsigned operands in response to the first configuration signal. In one embodiment the method comprising outputting a carry vector and a sum vector, and adding the carry vector and the sum vector provided by the output row of the CSA unit via a CPA unit consisting of a row of na full adder cells, wherein the carry input of the CPA unit is coupled to receive a first configuration signal to switch between processing of signed and unsigned two's complement operands.
摘要翻译：本发明涉及一种用于将由na位组成的第一操作数和由nx位组成的第二操作数相乘的乘法装置和方法。在一个实施例中，乘法装置包括具有nx行的CSA（CSA）单元，每个行包括用于计算两个单个位输入值的单位乘积的“与”门，以及用于将前一行的结果与后一行相加的加法器单元输出行，用于输出进位矢量和和矢量;以及逻辑电路，用于在nx-1个第一行的最高有效位置和在输出行的na-1个最低有效位置响应于在将选择性反转的单位产物输入到相应加法器单元之前的第一配置信号，用于响应于第一配置信号，有选择地在有符号二进制补码操作数的处理和无符号操作数之间切换CSA单元。在一个实施例中，该方法包括输出一个进位向量和一个和向量，并且通过由一行n1个全加器单元组成的CPA单元相加CSA单元的输出行提供的进位向量和和向量，其中进位 CPA单元的输入被耦合以接收第一配置信号以在有符号和无符号二进制补码操作数的处理之间切换。

6. 发明授权

US07386014B2 Shared backoff generation for 802.11E compliant WLAN communication devices 有权
标题翻译：针对802.11E兼容WLAN通信设备的共享后退生成
公开(公告)号：US07386014B2
公开(公告)日：2008-06-10
申请号：US11106775
申请日：2005-04-15
申请人： Ralf Flemming , Andreas Abt , Andre Schulze , Christian Wiencke
发明人： Ralf Flemming , Andreas Abt , Andre Schulze , Christian Wiencke
IPC分类号： H04J3/06
CPC分类号： H04W74/0808 , H04W28/14 , H04W84/12
摘要： A WLAN (Wireless Local Area Network) communication device including a first buffer, a second buffer and a shared backoff generator and corresponding methods and integrated circuit chips provided. The first buffer is for queuing first data packets to be transmitted by the WLAN communication device after a transmission channel has been idle for at least a first backoff time. The second buffer is for queuing second data packets to be transmitted by the WLAN communication device after the transmission channel has been idle for at least a second backoff time. The shared backoff generator is adapted to generate a first and a second backoff start value used to determine the first and second backoff times, respectively. Embodiments may reduce the hardware consumption and thus manufacturing and product costs.
摘要翻译：包括第一缓冲器，第二缓冲器和共享回退发生器的WLAN（无线局域网）通信设备以及提供的相应方法和集成电路芯片。第一缓冲器用于在传输信道空闲至少第一退避时间之后对由WLAN通信设备发送的第一数据分组进行排队。第二缓冲器用于在传输信道已经空闲至少第二退避时间之后对由WLAN通信设备发送的第二数据分组进行排队。共享后退发生器适于分别产生用于确定第一和第二退避时间的第一和第二退避起始值。实施例可以减少硬件消耗，从而减少制造和产品成本。

7. 发明申请

US20060114823A1 Shared backoff generation for 802.11E compliant WLAN communication devices 有权
标题翻译：针对802.11E兼容WLAN通信设备的共享后退生成
公开(公告)号：US20060114823A1
公开(公告)日：2006-06-01
申请号：US11106775
申请日：2005-04-15
申请人： Ralf Flemming , Andreas Abt , Andre Schulze , Christian Wiencke
发明人： Ralf Flemming , Andreas Abt , Andre Schulze , Christian Wiencke
IPC分类号： H04L12/26 , H04B7/00 , H04L12/413 , H04L1/00
CPC分类号： H04W74/0808 , H04W28/14 , H04W84/12
摘要： A WLAN (Wireless Local Area Network) communication device including a first buffer, a second buffer and a shared backoff generator and corresponding methods and integrated circuit chips provided. The first buffer is for queuing first data packets to be transmitted by the WLAN communication device after a transmission channel has been idle for at least a first backoff time. The second buffer is for queuing second data packets to be transmitted by the WLAN communication device after the transmission channel has been idle for at least a second backoff time. The shared backoff generator is adapted to generate a first and a second backoff start value used to determine the first and second backoff times, respectively. Embodiments may reduce the hardware consumption and thus manufacturing and product costs.
摘要翻译：包括第一缓冲器，第二缓冲器和共享回退发生器的WLAN（无线局域网）通信设备以及提供的相应方法和集成电路芯片。第一缓冲器用于在传输信道空闲至少第一退避时间之后对由WLAN通信设备发送的第一数据分组进行排队。第二缓冲器用于在传输信道已经空闲至少第二退避时间之后对由WLAN通信设备发送的第二数据分组进行排队。共享后退发生器适于分别产生用于确定第一和第二退避时间的第一和第二退避起始值。实施例可以减少硬件消耗，从而减少制造和产品成本。

8. 发明授权

US08667043B2 Method and apparatus for multiplying binary operands 有权
标题翻译：用于乘以二进制操作数的方法和装置
公开(公告)号：US08667043B2
公开(公告)日：2014-03-04
申请号：US12266315
申请日：2008-11-06
申请人： Christian Wiencke
发明人： Christian Wiencke
IPC分类号： G06F7/523
CPC分类号： G06F7/523 , G06F7/5306 , G06F2207/382
摘要： Method and apparatus for multiplying a signed first operand na bits and a signed second operand nb bits, wherein na and nb are different positive integer numbers, the method comprising generating single bit products of pairs of a single bit from the signed first operand and a single bit from the signed second operand with a logical AND function to produce na times nb single bit products, selectively inverting for the signed first operand and the signed second operands the single bit products of the first operand bit na-1 multiplied with the second operand bits 0 to nb-2, selectively inverting the single bit products of the signed second operand bits 0 to na-2 multiplied with the signed second operand bit nb-1, after the step of inverting adding the single bit products in accordance with their respective order for producing an intermediate product, and adding a ‘1’ bit value at bit positions nb-1, na-1 and na+nb-1 for receiving a final product.
摘要翻译：用于将有符号的第一操作数na位和带符号的第二操作数nb位相乘的方法和装置，其中na和nb是不同的正整数，该方法包括从签名的第一操作数生成单位对的单位产物和单符号从具有逻辑“和”功能的带符号的第二操作数开始，产生无效的单位乘积，对于有符号的第一操作数和有符号的第二操作数有选择地反相，第一操作数位na-1的单位乘积与第二操作数位相乘 0到nb-2，在反转步骤之后，根据它们各自的顺序反相添加单个位产物，选择性地将符号的第二操作数位0到na-2的单个比特乘积与有符号的第二操作数位nb-1相乘用于产生中间产品，并且在位置nb-1，na-1和na + nb-1处添加用于接收最终产品的“1”比特值。

9. 发明申请

US20130031154A1 SELF-TIMED MULTIPLIER 有权
标题翻译：自定义乘法器
公开(公告)号：US20130031154A1
公开(公告)日：2013-01-31
申请号：US13559832
申请日：2012-07-27
申请人： Christian Wiencke , Horst Diewald
发明人： Christian Wiencke , Horst Diewald
IPC分类号： G06F7/52
CPC分类号： G06F7/5312
摘要： A self-timed multiplier unit includes a multiplier and a clock generator. The multiplier has a first set of semiconductor circuits in a critical path. The clock generator has a second set of semiconductor circuits configured to control a clock period of said clock generator selected to set a clock period longer than the propagation delay through the critical path of the multiplier. The clock generator may include a delay circuit having a delay to set the clock period longer than the propagation delay through the critical path of said multiplier. The clock generator uses circuit with identical logical design including the same standard cells, the same logic design or the same floor plan. Close matching of these circuit causes the multiplier and the clock generator to experience the same PVT speed variations.
摘要翻译：自定时乘法器单元包括乘法器和时钟发生器。乘法器在关键路径中具有第一组半导体电路。时钟发生器具有第二组半导体电路，其被配置为控制所选择的所述时钟发生器的时钟周期，以设置比通过乘法器的关键路径的传播延迟更长的时钟周期。时钟发生器可以包括具有延迟的延迟电路，以将时钟周期设置为比通过所述乘法器的关键路径的传播延迟更长。时钟发生器使用具有相同逻辑设计的电路，包括相同的标准单元，相同的逻辑设计或相同的平面图。这些电路的紧密匹配使乘法器和时钟发生器经历相同的PVT速度变化。

10. 发明申请

US20090132630A1 METHOD AND APPARATUS FOR MULTIPLYING BINARY OPERANDS 有权
标题翻译：用于二进制运算的方法和装置
公开(公告)号：US20090132630A1
公开(公告)日：2009-05-21
申请号：US12266315
申请日：2008-11-06
申请人： Christian Wiencke
发明人： Christian Wiencke
IPC分类号： G06F7/52
CPC分类号： G06F7/523 , G06F7/5306 , G06F2207/382
摘要： Method and apparatus for multiplying a signed first operand na bits and a signed second operand nb bits, wherein na and nb are different positive integer numbers, the method comprising generating single bit products of pairs of a single bit from the signed first operand and a single bit from the signed second operand with a logical AND function to produce na times nb single bit products, selectively inverting for the signed first operand and the signed second operands the single bit products of the first operand bit na-1 multiplied with the second operand bits 0 to nb-2, selectively inverting the single bit products of the signed second operand bits 0 to na-2 multiplied with the signed second operand bit nb-1, after the step of inverting adding the single bit products in accordance with their respective order for producing an intermediate product, and adding a ‘1’ bit value at bit positions nb-1, na-1 and na+nb-1 for receiving a final product.
摘要翻译：用于将有符号的第一操作数na位和带符号的第二操作数nb位相乘的方法和装置，其中na和nb是不同的正整数，该方法包括从签名的第一操作数生成单位对的单位产物和单符号从具有逻辑“和”功能的带符号的第二操作数开始，产生无效的单位乘积，对于有符号的第一操作数和有符号的第二操作数有选择地反相，第一操作数位na-1的单位乘积与第二操作数位相乘 0到nb-2，在反转步骤之后，根据它们各自的顺序反相添加单个位产物，选择性地将符号的第二操作数位0到na-2的单个比特乘积与有符号的第二操作数位nb-1相乘用于产生中间产品，并且在位置nb-1，na-1和na + nb-1处添加用于接收最终产品的“1”比特值。

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