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1. 发明授权

US07933144B2 Component with a logic circuit arrangement with configurable functionality 有权
标题翻译：具有可配置功能的逻辑电路配置的组件
公开(公告)号：US07933144B2
公开(公告)日：2011-04-26
申请号：US10552657
申请日：2004-03-24
申请人： Joachim Bangert , Christian Siemers
发明人： Joachim Bangert , Christian Siemers
IPC分类号： G11C11/00
CPC分类号： H03K17/80 , H03K17/223
摘要： A component with a logic circuit arrangement with configurable functionality, includes several data lines (7), whereby at least a part of the data lines (7) is provided with at least one element (1) which may be switched between two states with different discrete resistances. The data line (7) is opened or closed by the element (1), depending on the switched state.
摘要翻译：具有具有可配置功能的逻辑电路布置的部件包括若干数据线（7），由此至少一部分数据线（7）设置有至少一个元件（1），其可以在具有不同的两个状态之间切换离散电阻。根据切换状态，数据线（7）由元件（1）打开或关闭。

2. 发明授权

US07161383B2 Programmable logic device 有权
标题翻译：可编程逻辑器件
公开(公告)号：US07161383B2
公开(公告)日：2007-01-09
申请号：US10532643
申请日：2003-10-23
申请人： Christian Siemers
发明人： Christian Siemers
IPC分类号： H03K19/177
CPC分类号： H03K19/17752 , H03K19/17736 , H03K19/17756 , H03K19/17796
摘要： The invention relates to a programmable logic device (7) comprising several logic blocks (3A to 3D) with configurable characteristics, elements for linking the logic blocks to one another and a processing unit (4) and an input/output unit (5). In addition, the linking elements have at least one configurable changeover logic block, enabling the logic blocks (3A to 3D) to be re-configured during the operation of the logic device (7). Said changeover logic block is used for the configuration of at least one of the re-configurable logic blocks (3A to 3D) and its connection to other blocks and/or its connection to the processing unit (4) and/or to the input/output unit (5).
摘要翻译：本发明涉及一种可编程逻辑器件（7），其包括具有可配置特性的多个逻辑块（3A至3D），用于将逻辑块彼此链接的元件以及处理单元（4）和输入/输出单元（5））。另外，连接元件具有至少一个可配置的转换逻辑块，使得在逻辑器件（7）的操作期间能够重新配置逻辑块（3A至3D）。所述切换逻辑块用于配置至少一个可重配置逻辑块（3A至3D）及其与其他块的连接和/或其与处理单元（4）的连接和/或至输入/输出单元（5）。

3. 发明授权

US07028162B2 Configurable processing block capable of interacting with external hardware 有权
标题翻译：可配置的处理块能够与外部硬件进行交互
公开(公告)号：US07028162B2
公开(公告)日：2006-04-11
申请号：US09816926
申请日：2001-03-23
申请人： Ralf Arnold , Helge Kleve , Christian Siemers
发明人： Ralf Arnold , Helge Kleve , Christian Siemers
IPC分类号： G06F15/177 , G06F13/00
CPC分类号： G06F9/3001 , G06F15/7867
摘要： The configurable hardware block is designed to read data stored in a memory according to its configuration, to process the read-out data arithmetically and/or logically and to write the data representing the result of the processing into the memory. The hardware block is capable of interacting with external hardware, thereby providing a flexible and universally applicable hardware block.
摘要翻译：可配置硬件块被设计为根据其配置来读取存储在存储器中的数据，以数学和/或逻辑方式处理读出数据，并将表示处理结果的数据写入存储器。硬件块能够与外部硬件进行交互，从而提供灵活且普遍适用的硬件块。

4. 发明授权

US07355439B2 Configurable logic circuit arrangement 有权
标题翻译：可配置逻辑电路布置
公开(公告)号：US07355439B2
公开(公告)日：2008-04-08
申请号：US10571790
申请日：2004-10-07
申请人： Joachim Bangert , Christian Siemers
发明人： Joachim Bangert , Christian Siemers
IPC分类号： H03K19/173 , G06F7/38
CPC分类号： H03K19/1737 , H04J3/04
摘要： A configurable logic circuit arrangement includes at least one multiplexer for switching logic signals. The multiplexer includes one or more data inputs and one or more control signal inputs. The at least one multiplexer (8, 12, 13) can be configured by one or more external control signal transmitter elements of the circuit arrangement during the operation of the circuit in a run-time variable manner by configuration signals that are applied to the control inputs and forwards the logical signals that are applied to the data inputs during operation of the circuit in a run-time variable manner.
摘要翻译：可配置逻辑电路装置包括用于切换逻辑信号的至少一个多路复用器。多路复用器包括一个或多个数据输入和一个或多个控制信号输入。所述至少一个多路复用器（8,12,13）可以由电路装置的一个或多个外部控制信号发射器元件在运行时间可变方式的电路运行期间通过施加到控制器的配置信号来配置在运行时可变的方式输入和转发在电路运行期间应用于数据输入的逻辑信号。

5. 发明申请

US20070024319A1 Configurable logic circuit arangement 有权
标题翻译：可配置逻辑电路布置
公开(公告)号：US20070024319A1
公开(公告)日：2007-02-01
申请号：US10571790
申请日：2004-10-07
申请人： Joachim Bangert , Christian Siemers
发明人： Joachim Bangert , Christian Siemers
IPC分类号： H03K19/177
CPC分类号： H03K19/1737 , H04J3/04
摘要： A configurable logic circuit arrangement includes at least one multiplexer for switching logic signals. The multiplexer includes one or more data inputs and one or more control signal inputs. The at least one multiplexer (8, 12, 13) can be configured by one or more external control signal transmitter elements of the circuit arrangement during the operation of the circuit in a run-time variable manner by configuration signals that are applied to the control inputs and forwards the logical signals that are applied to the data inputs during operation of the circuit in a run-time variable manner.
摘要翻译：可配置逻辑电路装置包括用于切换逻辑信号的至少一个多路复用器。多路复用器包括一个或多个数据输入和一个或多个控制信号输入。所述至少一个多路复用器（8,12,13）可以由电路装置的一个或多个外部控制信号发射器元件在运行时间可变方式的电路运行期间通过施加到控制器的配置信号来配置在运行时可变的方式输入和转发在电路运行期间应用于数据输入的逻辑信号。

6. 发明授权

US07509479B2 Reconfigurable global cellular automaton with RAM blocks coupled to input and output feedback crossbar switches receiving clock counter value from sequence control unit 有权
标题翻译：可重配置的全局细胞自动机，具有耦合到输入和输出反馈的RAM块交叉开关，从序列控制单元接收时钟计数器值
公开(公告)号：US07509479B2
公开(公告)日：2009-03-24
申请号：US11662469
申请日：2005-09-08
申请人： Christian Siemers
发明人： Christian Siemers
IPC分类号： G06F13/00
CPC分类号： G06F15/7867
摘要： The invention relates to a computer containing a RAM-based primary part (Ht) with a stucturable RAM unit (2). On the input side, a first crossbar switch (1) is located upstream of said unit and a second crossbar switch (3) is located downstream. Address signals (18, 13) can be supplied from the first crossbar switch (1) to the RAN unit (2) or the second crossbar switch (3). Output signals (10) can be fed back from the second crossbar switch to the first crossbar switch (1) and can be output. An additional control part (St) for a configurable job sequencing of the primary part (Ht) comprises a counter unit (4) that is synchronised with the first crossbar switch (1) to create counter reading signals (12) for the first and second crossbar switch (1 and 3). The computer is particularly suitable for integrating a global cellular automaton (GCA).
摘要翻译：本发明涉及一种包含基于RAM的主要部分（Ht）的计算机，其具有可稳定的RAM单元（2）。在输入侧，第一交叉开关（1）位于所述单元的上游，并且第二交叉开关（3）位于下游。地址信号（18,13）可以从第一交叉开关（1）提供给RAN单元（2）或第二交叉开关（3）。输出信号（10）可从第二交叉开关反馈到第一交叉开关（1）并输出。用于主要部分（Ht）的可配置作业排序的附加控制部分（St）包括与第一交叉开关（1）同步的计数器单元（4），以产生第一和第二部分的计数器读取信号（12）横杆开关（1和3）。该计算机特别适用于集成全球细胞自动机（GCA）。

7. 发明申请

US20070260805A1 Computer with a Reconfigurable Architecture for Integrating a Global Cellular Automaton 有权
标题翻译：具有用于集成全球细胞自动机的可重构架构的计算机
公开(公告)号：US20070260805A1
公开(公告)日：2007-11-08
申请号：US11662469
申请日：2005-09-08
申请人： Christian Siemers
发明人： Christian Siemers
IPC分类号： G06F13/00
CPC分类号： G06F15/7867
摘要： A computer containing a RAM-based primary part (Ht) with a stucturable RAM unit (2). On the input side, a first crossbar switch (1) is located upstream of the unit and a second crossbar switch (3) is located downstream. Address signals (18, 13) can be supplied from the first crossbar switch (1) to the RAM unit (2) or the second crossbar switch (3). Output signals (10) can be fed back from the second crossbar switch to the first crossbar switch (1) and can be output. An additional control part (St) for a configurable job sequencing of the primary part (Ht) comprises a counter unit (4) that is synchronized with the first crossbar switch (1) to create counter reading signals (12) for the first and second crossbar switch (1 and 3). The computer is particularly suitable for integrating a global cellular automaton (GCA).
摘要翻译：包含基于RAM的主要部件（Ht）的计算机，其具有可固定的RAM单元（2）。在输入侧，第一交叉开关（1）位于该单元的上游，并且第二交叉开关（3）位于下游。地址信号（18,13）可以从第一交叉开关（1）提供给RAM单元（2）或第二交叉开关（3）。输出信号（10）可从第二交叉开关反馈到第一交叉开关（1）并输出。用于主要部分（Ht）的可配置作业排序的附加控制部分（St）包括与第一交叉开关（1）同步的计数器单元（4），以产生第一和第二部分的计数器读取信号（12）横杆开关（1和3）。该计算机特别适用于集成全球细胞自动机（GCA）。

8. 发明授权

US06996709B2 Method for configuring a configurable hardware block by configuring configurable connections provided around a given type of subunit 有权
标题翻译：通过配置围绕给定类型的子单元提供的可配置连接来配置可配置硬件块的方法
公开(公告)号：US06996709B2
公开(公告)日：2006-02-07
申请号：US09815659
申请日：2001-03-23
申请人： Ralf Arnold , Helge Kleve , Christian Siemers
发明人： Ralf Arnold , Helge Kleve , Christian Siemers
IPC分类号： G06F9/00
CPC分类号： G06F9/3001 , G06F9/3885 , G06F9/3897 , G06F15/7867
摘要： A method for configuring a configurable hardware block includes implementing commands and/or command sequences of a program to be executed. The implementing step includes ascertaining a given type of subunit of a configurable hardware block, the given type of subunit being required for executing a respective command, selecting, if available, a subunit of the given type of subunit, configuring configurable connections provided around the subunit selected in the selecting step, if the subunit of the given type of subunit is found in the selecting step, and ascertaining configuration data with the step of implementing the commands and/or command sequences. The configurable hardware block is configured by using the configuration data.
摘要翻译：用于配置可配置硬件块的方法包括实现要执行的程序的命令和/或命令序列。实施步骤包括确定可配置硬件块的给定类型的子单元，执行相应命令所需的给定类型的子单元，如果可用，选择给定类型的子单元的子单元，配置在子单元周围提供的可配置连接如果在选择步骤中找到给定类型的子单元的子单元，并且通过实现命令和/或命令序列的步骤来确定配置数据，则在选择步骤中选择。可配置的硬件块通过使用配置数据进行配置。

9. 发明申请

US20100019830A1 Component With a Functionally-Configurable Circuit Arrangement 有权
标题翻译：具有功能可配置电路布置的组件
公开(公告)号：US20100019830A1
公开(公告)日：2010-01-28
申请号：US11997501
申请日：2006-07-19
申请人： Joachim Bangert , Markus Köchy , Christian Siemers
发明人： Joachim Bangert , Markus Köchy , Christian Siemers
IPC分类号： H03K17/60
CPC分类号： H03K19/1736
摘要： A component with a functionally-configurable circuit arrangement, has a first switch group with a voltage-dependent switching on or off of a data line and at least one second switch group generating two discrete output voltages separated by an increase in voltage and the switch states for the discrete output voltages may be stored in non-volatile memory. The switching on or off of the data line is determined by the switch state of the first switch group and a third switch group (11) is provided to increase the voltage increase between the first switch group (17) and the second switch group (3).
摘要翻译：具有功能可配置电路布置的部件具有第一开关组，其具有与数据线相关的导通或关断的电压依赖性，以及至少一个第二开关组，其产生由电压增加和开关状态分开的两个离散输出电压因为离散输出电压可以存储在非易失性存储器中。数据线的接通或断开由第一开关组的开关状态确定，并且提供第三开关组（11）以增加第一开关组（17）和第二开关组（3）之间的电压增加）。

10. 发明授权

US07352205B2 Reconfigurable switching device parallel calculation of any particular algorithms 有权
标题翻译：可重配置的交换设备并行计算任何特定的算法
公开(公告)号：US07352205B2
公开(公告)日：2008-04-01
申请号：US10588860
申请日：2005-02-07
申请人： Christian Siemers , Christian Wiegand
发明人： Christian Siemers , Christian Wiegand
IPC分类号： H03K19/173
CPC分类号： G06F15/7867
摘要： A configurable architecture of a calculation device includes at least one individual configurable and/or reconfigurable switching device, whereby the output variables thereof form a time point tn-1 and the input variables of the switching device form a time point tn. Elements are provided in order to control the output variables in a clocked manner and to store the output variables of the switching device between the time points tn-1 and tn.
摘要翻译：计算设备的可配置架构包括至少一个单独的可配置和/或可重新配置的切换设备，由此其输出变量形成时间点t 1-n 1，并且切换设备的输入变量形成时间点t 。提供元件以便以时钟方式控制输出变量并且在时间点t 1和n 2之间存储开关器件的输出变量。

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