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1. 发明授权

US5299087A Overload protection circuit 失效
标题翻译：过载保护电路
公开(公告)号：US5299087A
公开(公告)日：1994-03-29
申请号：US731593
申请日：1991-07-17
申请人： Yvan Fermier , Michel Ferry , Christian Jacquart , Pierre Vachee
发明人： Yvan Fermier , Michel Ferry , Christian Jacquart , Pierre Vachee
IPC分类号： G06F1/30 , H02H3/08 , H02H3/087 , H02J13/00 , H02H3/093
CPC分类号： H02H3/087 , H03F2200/426
摘要： The overload protection circuit 12 comprises a resistor bridge 20 with a low impedance sensing resistor r and high impedance resistors R1 to R4 which generates voltages Va and Vb at the inputs 32 and 34 of a comparator 22. Voltage Vb depend upon the value of the load current so that the comparator provides at its output 36 a control signal for opening the switching device 24 comprising a field effect transistor when the load current exceeds a maximum value. Resistor R5 reinforces the effect of the control signal. This circuit can be used in a system which comprises a central power supply unit 8 which powers a plurality of devices such as 4. The status of the circuit 12 is reported to the system 8 though line 14 and circuit 12 comprises a control circuit 26 which is responsive to set and reset control signals on lines 14 and 18 from the unit 8 to close or open the switch 26.
摘要翻译：过载保护电路12包括具有低阻抗感测电阻器r的电阻器桥20和在比较器22的输入端32和34处产生电压Va和Vb的高阻抗电阻器R1至R4。电压Vb取决于负载的值使得比较器在其输出端36提供用于在负载电流超过最大值时打开包括场效应晶体管的开关器件24的控制信号。电阻R5加强了控制信号的影响。该电路可以用于包括对多个设备（例如4）供电的中央电源单元8的系统中。电路12的状态通过线路14被报告给系统8，电路12包括控制电路26，控制电路26 响应于来自单元8的线路14和18上的设置和复位控制信号以关闭或打开开关26。

2. 发明授权

US4115660A Telephone line interfacing circuit with directional transfer of ringing current and off-hook indications 失效
标题翻译：电话线接口电路，具有振铃电流和摘机指示的定向传输
公开(公告)号：US4115660A
公开(公告)日：1978-09-19
申请号：US831329
申请日：1977-09-07
申请人： Alain Croisier , Christian Jacquart
发明人： Alain Croisier , Christian Jacquart
IPC分类号： H04M19/00 , H04M3/18
CPC分类号： H04L25/0268 , H04M19/008
摘要： A circuit for interfacing an AF line to a central unit makes use of an RF transformer Tr. Said transformer is so arranged that the source AF signal to be transmitted modulates an RF carrier generated in a primary winding of the transformer and the resulting modulated signal in the secondary winding is demodulated before being transmitted to a line which is thereby linked to the source.
摘要翻译：用于将AF线连接到中央单元的电路使用RF变压器Tr。所述变压器被布置成使得待传输的源AF信号调制在变压器的初级绕组中产生的RF载波，并且在次级绕组中产生的调制信号被传送到由此链接到源极的线之前被解调。

3. 发明授权

US4731829A Circuit for detecting current variations 失效
标题翻译：用于检测电流变化的电路
公开(公告)号：US4731829A
公开(公告)日：1988-03-15
申请号：US30263
申请日：1987-03-24
申请人： Yves A. Bonnet , Christian Jacquart
发明人： Yves A. Bonnet , Christian Jacquart
IPC分类号： H04Q3/72 , H04M3/22
CPC分类号： H04M3/2272
摘要： The circuit of the present invention detects variations of a current I.sub.L flowing in a telephone line LL. A low-value resistor r is connected in series with line LL. A constant voltage generator is connected across this resistor. The current Is applied to resistor r by the contant voltage generator varies as a function of I.sub.L. This being so, a measurement of the variations of Is will reflect variations of I.sub.L and, therefore, can be used to detect both amplitude and directional variations of I.sub.L.
摘要翻译：本发明的电路检测在电话线LL中流动的电流IL的变化。低电阻r与线路LL串联连接。恒定电压发生器连接在该电阻上。由电流发生器施加到电阻器r的电流随IL的变化而变化。这样，Is的变化的测量将反映IL的变化，因此可以用于检测IL的幅度和方向变化。

4. 发明授权

US5001480A Analog-to-digital and digital-to-analog conversion system and echo cancellation device including the same 失效
标题翻译：模拟数字和数模转换系统以及回波消除装置包括相同的
公开(公告)号：US5001480A
公开(公告)日：1991-03-19
申请号：US258936
申请日：1988-10-17
申请人： Michel Ferry , Christian Jacquart
发明人： Michel Ferry , Christian Jacquart
IPC分类号： H03M1/02 , G06J1/00 , H03M1/00 , H04B3/23
CPC分类号： H04B3/23 , G06J1/00 , H03M1/02 , H03M1/46 , H04B3/238
摘要： A conversion system is disclosed for performing either an analog-to-digital A/D conversion associated with an amplification step or a digital-to-analog D/A conversion associated with an attenuation step. The system includes apparatus (115) for receiving a input digital word to be processed, i.e. converted into analog and then attenuated, and apparatus (165) for receiving a input analog value to be processed, i.e. amplified for scaling purposes and then converted into digital. It also includes a digital-to-analog D/A converter (110), an attenuator (120) for attenuating the analog output of D/A converter (110), and a comparator (150) for comparing the value of the input analog value to be processed and the output of said attenuator (120). The processing of the D/A-attenuation process is performed by both the D/A converter (110) and attenuator (120). In order to achieve the A/D-amplification process, the system further includes generator apparatus (140) for generating a sequence of digital words to the D/A converter (110), and storage apparatus (220) for storing among this sequence, the digital value that minimizes the difference between both input of comparator (150). This digital value is extracted as being the digital representation of the amplified analog input value. Since both A/D-amplification and D/A-attenuation processings involve the same physical components, both processing have transfer function exactly inverse of one another. The typical use of this circuit is in echo cancellation technique.

5. 发明授权

US4656643A Line interface circuit 失效
标题翻译：线路接口电路
公开(公告)号：US4656643A
公开(公告)日：1987-04-07
申请号：US764460
申请日：1985-08-12
申请人： Michel Geneste , Christian Jacquart
发明人： Michel Geneste , Christian Jacquart
IPC分类号： H04L1/24 , H04L25/02 , H04L29/14
CPC分类号： H04L1/243
摘要： A line interface circuit for connecting the transmit and receive ports of a transmitter to transmit lines (LX) and receive lines (LR), respectively. The interface circuit includes a transistorized differential amplifier provided with two load circuits comprising resistors and diodes connected in series, and logic control means for selectively switching power to either load circuit. One of the load circuits drives the transmit line (LX) while the other drives the receive ports of the transmitter. Switching the load circuits makes it possible to use the interface circuit either to drive the transmit line (LX) or to loop the output signal from the transmitter back to the receive input thereof, while loading the transmit line (LX) with its characteristic impedance.
摘要翻译：一种用于将发射机的发射和接收端口分别连接到发射线路（LX）和接收线路（LR）的线路接口电路。该接口电路包括一个晶体管化的差分放大器，该差分放大器设置有包括串联连接的电阻和二极管的两个负载电路，以及逻辑控制装置，用于选择性地将功率切换到负载电路。其中一个负载电路驱动发射线（LX），而另一个驱动发射机的接收端口。切换负载电路使得可以使用接口电路来驱动发射线（LX）或将来自发射机的输出信号回送到其接收输入，同时以其特征阻抗加载发射线（LX）。

6. 发明授权

US4315307A Switching device and switched-type power supply using the same 失效
标题翻译：开关器件和开关式电源使用相同
公开(公告)号：US4315307A
公开(公告)日：1982-02-09
申请号：US155288
申请日：1980-06-02
申请人： Christian Jacquart
发明人： Christian Jacquart
IPC分类号： H03K17/04 , H01L27/07 , H02M3/337 , H03K17/567 , H02M7/537
CPC分类号： H02M3/3372 , H01L27/0716 , H03K17/567
摘要： Signals to the base of a bipolar transistor and to the gate of a parallel - connected FET are timed to turn on the two transistors simultaneously and to turn off the bipolar transistor before the FET. The shorter switching time of the FET is combined with the low resistance of the bipolar transistor to provide a switch that is particularly useful in a switched-type power supply with increased switched frequency.
摘要翻译：到双极晶体管的基极和并联连接的FET的栅极的信号被定时以同时导通两个晶体管并且在FET之前关闭双极晶体管。 FET的较短开关时间与双极晶体管的低电阻相结合，以提供一种开关，该开关在具有增加的开关频率的开关式电源中特别有用。

7. 发明授权

US5272584A Hot-plugging circuit for the interconnection of cards to boards 失效
标题翻译：热插拔电路，用于将卡互连到电路板
公开(公告)号：US5272584A
公开(公告)日：1993-12-21
申请号：US792329
申请日：1991-11-12
申请人： Pierre Austruy , Jean-Paul Conjeaud , Patrick Massi , Christian Jacquart
发明人： Pierre Austruy , Jean-Paul Conjeaud , Patrick Massi , Christian Jacquart
IPC分类号： G06F1/18 , G06F1/26 , G06F3/00 , G06K19/07 , H01R12/16 , H02H9/00
CPC分类号： H02H9/004 , Y10S323/908
摘要： A hot plug circuit insuring that the plugging of cards to a board is performed in the hot-plug mode when the cards are supplied from a common power supply located on one of the cards or on the board. This circuit (62) limits the surge current generated at the interconnection of first circuits (30) arranged on a first card (1) and powered by a supply device (2) providing a first supply voltage (ground) on a first supply line (36) and a second supply voltage (+V) on a second supply line (34), with second circuit (24) on a second card powered by the supply device (2) through a third supply line (74) and fourth supply line (76). The surge current results from the charge of a decoupling capacitor of capacitance Cd arranged on the second card between the third and fourth supply lines when the cards are interconnected through an interconnecting arrangement (14, 12, 22). The hot plug circuit comprises a controlled ramp generation device connected to the first and second supply lines and activated when the connection between the first and third supply line is completed through the connecting arrangement to start the generation on the fourth supply line of a first ramp voltage Vb derived from the voltages on the first and second supply lines, said ramp voltage having an adjustable slope a=dVb/dt, whereby the surge current i which is equal to a.Cd can be limited to a desired value by adjusting the slope value a.

8. 发明授权

US4746903A Parallel algorithmic digital to analog converter 失效
标题翻译：并行算法数模转换器
公开(公告)号：US4746903A
公开(公告)日：1988-05-24
申请号：US942745
申请日：1986-12-17
申请人： Jean-Christophe Czarniak , Michel F. Ferry , Christian Jacquart
发明人： Jean-Christophe Czarniak , Michel F. Ferry , Christian Jacquart
IPC分类号： H03M1/68 , H03M1/00 , H03M1/66
CPC分类号： H03M1/68 , H03M1/667
摘要： A digital to analog converter for converting an N-bit digital word into its analog representation including means for splitting the N bits into n sections of N/n bits each. For instance a 12-bit word is split into an odd section and an even section which are processed independently and in parallel. This results in two partial results, V.sub.i and V.sub.p, respectively, representative of the odd and even bit sections. The last step of the conversion is the action of the two partial results V.sub.i and V.sub.p to provide the analog representation of the 12-bit word. Few operators are required to process each section because each bit is converted sequentially. This provides a low cost, compact and simple converter, moreover, since few operators are required, it may be advantageous to use high precision operators as disclosed.
摘要翻译：一种用于将N位数字字转换为其模拟表示的数模转换器，包括用于将N位分成n个N / n位的各部分的装置。例如，一个12位字被分为奇数部分和偶数部分，它们是独立和并行处理的。这导致两个部分结果，Vi和Vp分别代表奇数和偶数位部分。转换的最后一步是两个部分结果Vi和Vp的动作来提供12位字的模拟表示。每个部分都需要很少的处理器，因为每个位都是顺序转换的。这提供了低成本，紧凑且简单的转换器，此外，由于需要很少的操作者，所以使用所公开的高精度操作器可能是有利的。

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