专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20090109198A1 BUFFER AMPLIFIER INCLUDED IN DISPLAY DRIVER AND METHOD OF GENERATING DRIVING VOLTAGES USING THE SAME 有权
标题翻译：包括在显示驱动器中的缓冲放大器及使用其产生驱动电压的方法
公开(公告)号：US20090109198A1
公开(公告)日：2009-04-30
申请号：US12243007
申请日：2008-10-01
申请人： Hyung-tae KIM , Soo-ik CHA , Chon-wook PARK
发明人： Hyung-tae KIM , Soo-ik CHA , Chon-wook PARK
IPC分类号： G06F3/038
CPC分类号： G09G3/2011 , G09G3/006 , G09G3/20 , G09G2310/027 , G09G2310/0291 , G09G2320/0233
摘要： A method of generating a driving voltage includes inputting a test gradation voltage to a first input terminal and a second input terminal of a buffer, latching the logic level of a test driving voltage output from an output terminal of the buffer, setting the buffer to a first type when the logic level of the test driving voltage is high level and setting the buffer to a second type when the logic level of the test driving voltage is low level, and operating the buffer set to the first type or the second type to generate a driving voltage corresponding to a gradation voltage.
摘要翻译：产生驱动电压的方法包括将测试灰度电压输入到缓冲器的第一输入端和第二输入端，锁存从缓冲器的输出端输出的测试驱动电压的逻辑电平，将缓冲器设置为当测试驱动电压的逻辑电平为低电平时，测试驱动电压的逻辑电平为高电平并将缓冲器设置为第二类型，并且将缓冲器设置为第一类型或第二类型以产生对应于灰度电压的驱动电压。

2. 发明授权

US08558824B2 Buffer amplifier included in display driver and method of generating driving voltages using the same 有权
标题翻译：显示驱动器中包括的缓冲放大器和使用其的产生驱动电压的方法
公开(公告)号：US08558824B2
公开(公告)日：2013-10-15
申请号：US12243007
申请日：2008-10-01
申请人： Hyung-tae Kim , Soo-ik Cha , Chon-wook Park
发明人： Hyung-tae Kim , Soo-ik Cha , Chon-wook Park
IPC分类号： G06F3/038 , G09G5/00
CPC分类号： G09G3/2011 , G09G3/006 , G09G3/20 , G09G2310/027 , G09G2310/0291 , G09G2320/0233
摘要： A method of generating a driving voltage includes inputting a test gradation voltage to a first input terminal and a second input terminal of a buffer, latching the logic level of a test driving voltage output from an output terminal of the buffer, setting the buffer to a first type when the logic level of the test driving voltage is high level and setting the buffer to a second type when the logic level of the test driving voltage is low level, and operating the buffer set to the first type or the second type to generate a driving voltage corresponding to a gradation voltage.
摘要翻译：产生驱动电压的方法包括将测试灰度电压输入到缓冲器的第一输入端和第二输入端，锁存从缓冲器的输出端输出的测试驱动电压的逻辑电平，将缓冲器设置为当测试驱动电压的逻辑电平为低电平时，测试驱动电压的逻辑电平为高电平并将缓冲器设置为第二类型，并且将缓冲器设置为第一类型或第二类型以产生对应于灰度电压的驱动电压。

3. 发明申请

US20100020114A1 DISPLAY DRIVER INTEGRATED CIRCUIT INCLUDING PRE-DECODER AND METHOD OF OPERATING THE SAME 审中-公开
标题翻译：显示驱动器集成电路，包括预解码器及其操作方法
公开(公告)号：US20100020114A1
公开(公告)日：2010-01-28
申请号：US12500225
申请日：2009-07-09
申请人： Woo-nyoung Lee , Chang-hwe Choi , Chon-wook Park
发明人： Woo-nyoung Lee , Chang-hwe Choi , Chon-wook Park
IPC分类号： G09G5/10
CPC分类号： G09G3/3688 , G09G3/2011
摘要： A display driver integrated circuit (IC) includes a grayscale voltage generator, a main decoder unit, a pre-decoder unit, and an output buffer unit. The grayscale voltage generator is configured to receive at least one gamma reference voltage and generate a plurality of grayscale voltages. The main decoder unit is configured to receive the grayscale voltages and data, decode the data, and selectively output a grayscale voltage based on the decoded result. The pre-decoder unit is configured to decode part of the data and output a precharge voltage. The output buffer unit is configured to sequentially receive an output of the pre-decoder unit and an output of the main-decoder unit, and output grayscale data used for driving a display device.
摘要翻译：显示驱动器集成电路（IC）包括灰度级电压发生器，主解码器单元，预解码器单元和输出缓冲器单元。灰度电压发生器被配置为接收至少一个伽马参考电压并产生多个灰度级电压。主解码器单元被配置为接收灰度电压和数据，解码数据，并且基于解码结果选择性地输出灰度电压。预解码器单元被配置为对部分数据进行解码并输出预充电电压。输出缓冲器单元被配置为顺序地接收预解码器单元的输出和主解码器单元的输出，以及输出用于驱动显示设备的灰度数据。

4. 发明申请

US20080180174A1 Output buffer with a controlled slew rate offset and source driver including the same 审中-公开
标题翻译：具有受控转换速率偏移的输出缓冲器和包含相同的源驱动器
公开(公告)号：US20080180174A1
公开(公告)日：2008-07-31
申请号：US12000155
申请日：2007-12-10
申请人： Hyung-tae KIM , Chang-sig KANG , Chon-wook PARK
发明人： Hyung-tae KIM , Chang-sig KANG , Chon-wook PARK
IPC分类号： H03F3/45
CPC分类号： H03F3/45192 , H03F1/083 , H03F3/3022 , H03F2203/30015 , H03F2203/45091 , H03F2203/45248 , H03F2203/45626
摘要： Example embodiments relate to an output buffer having a differential input circuit configured to convert a differential voltage signal input through a positive input terminal and a negative input terminal into a differential current signal, and configured to output the differential current signal. The differential input circuit may include a plurality of PMOS transistors and a plurality of NMOS transistors. The output buffer may further include a slew rate matching circuit configured to compensate for a difference between components of a first parasitic capacitor formed around the plurality of PMOS transistors and components of a second parasitic capacitor formed around the plurality of NMOS transistors.
摘要翻译：示例实施例涉及具有差分输入电路的输出缓冲器，该差分输入电路被配置为将通过正输入端和负输入端输入的差分电压信号转换为差分电流信号，并且被配置为输出差分电流信号。差分输入电路可以包括多个PMOS晶体管和多个NMOS晶体管。输出缓冲器还可以包括压摆率匹配电路，其被配置为补偿在多个PMOS晶体管周围形成的第一寄生电容器的分量与形成在多个NMOS晶体管周围的第二寄生电容器的分量之间的差异。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式