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1. 发明授权

US06653245B2 Method for liquid phase deposition 失效
标题翻译：液相沉积方法
公开(公告)号：US06653245B2
公开(公告)日：2003-11-25
申请号：US09874108
申请日：2001-06-06
申请人： Muh-Wang Liang , Pang-Min Chiang , Chen Max , Jen-Rong Huang , Ching-Fa Yeh
发明人： Muh-Wang Liang , Pang-Min Chiang , Chen Max , Jen-Rong Huang , Ching-Fa Yeh
IPC分类号： H01L2131
CPC分类号： H01L21/67086 , H01L21/316 , Y10T137/4643 , Y10T137/4891 , Y10T137/5386 , Y10T137/5474 , Y10T137/8593 , Y10T307/779
摘要： A method for liquid phase deposition, including the steps of providing at least two raw materials from at least two supply devices of a saturation reaction system into a mixture trough and stirring until saturation occurs, filtering out unnecessary solid-state particles, and providing saturated and filtered liquid into an over-saturation reaction trough of a steady-flow over-saturation loop reaction system and stopping the saturated and filtered liquid when the over-saturation reaction trough is filled and the saturated and filtered liquid over-flows into a liquid level control trough to a pre-determined level. The method also includes the steps of providing a substrate in the over-saturation reaction trough, providing reactants from at least two supply devices into the over-saturation reaction trough, and depositing a thin film onto the substrate when the saturated liquid becomes over-saturated.
摘要翻译：一种用于液相沉积的方法，包括以下步骤：将饱和反应体系的至少两个供应装置的至少两种原料提供到混合物槽中，并搅拌直到饱和发生，过滤不需要的固态颗粒，并提供饱和和过滤液体进入稳流过饱和环路反应系统的过饱和反应槽，当过饱和反应槽填满时停止饱和和过滤的液体，饱和和过滤的液体过量流入液位控制低谷达到预定水平。该方法还包括以下步骤：在过饱和反应槽中提供衬底，将反应物从至少两个供应装置提供到过饱和反应槽中，并且当饱和液体变得过度饱和时，将薄膜沉积到衬底上。

2. 发明授权

US06294832B1 Semiconductor device having structure of copper interconnect/barrier dielectric liner/low-k dielectric trench and its fabrication method 有权
标题翻译：具有铜互连/阻挡电介质衬垫/低k电介质沟槽结构的半导体器件及其制造方法
公开(公告)号：US06294832B1
公开(公告)日：2001-09-25
申请号：US09546539
申请日：2000-04-10
申请人： Ching-Fa Yeh , Yueh-Chuan Lee , Kwo-Hau Wu , Yuh-Ching Su
发明人： Ching-Fa Yeh , Yueh-Chuan Lee , Kwo-Hau Wu , Yuh-Ching Su
IPC分类号： H01L2348
CPC分类号： H01L21/02131 , H01L21/0214 , H01L21/02282 , H01L21/02321 , H01L21/0234 , H01L21/3122 , H01L21/3124 , H01L21/31629 , H01L21/76826 , H01L21/76828 , H01L21/76831 , H01L21/76835 , H01L23/53238 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： The present invention is related to a interconnection structure with Cu interconnects and low-k dielectric, in which a barrier dielectric liner made of a nitrogen-containing liquid-phase-deposition (LPD) fluorosilicate glass (FSG) film is used to replace a barrier metal layer and an oxide liner.
摘要翻译：本发明涉及具有Cu互连和低k电介质的互连结构，其中使用由含氮液相沉积（LPD）氟硅酸盐玻璃（FSG）膜制成的阻挡介电衬垫来代替阻挡层金属层和氧化物衬垫。

3. 发明授权

US6039857A Method for forming a polyoxide film on doped polysilicon by anodization 有权
标题翻译：通过阳极氧化在掺杂多晶硅上形成多氧化物膜的方法
公开(公告)号：US6039857A
公开(公告)日：2000-03-21
申请号：US188062
申请日：1998-11-09
申请人： Ching-Fa Yeh , Jeng-Shu Liu
发明人： Ching-Fa Yeh , Jeng-Shu Liu
IPC分类号： C25D11/32 , H01L21/28 , H01L21/321 , C25D5/18
CPC分类号： C25D11/32 , H01L21/28273 , H01L21/32105
摘要： The present invention relates to a method for forming a polyoxide film on a doped polysilicon layer, which is suitable for use as an inter-polysilicon polyoxide film between a doped polysilicon floating gate and a doped polysilicon control gate. The method includes conducting an electrolytic reaction at a room, temperature such that a polyoxide layer is formed on a doped polysilicon layer acting as an anode. The polyoxide layer is preferably further subjected with a rapid thermal processing to improve its electrical characteristics.
摘要翻译：本发明涉及在掺杂多晶硅层上形成多氧化物膜的方法，其适用于掺杂多晶硅浮置栅极和掺杂多晶硅控制栅极之间的多晶硅间多氧化物膜。该方法包括在室内进行电解反应，使得在作为阳极的掺杂多晶硅层上形成多氧化物层。优选地，通过快速热处理进一步对多氧化物层进行处理以改善其电特性。

4. 发明授权

US5661051A Method for fabricating a polysilicon transistor having a buried-gate structure 失效
标题翻译：一种具有掩埋栅结构的多晶硅晶体管的制造方法
公开(公告)号：US5661051A
公开(公告)日：1997-08-26
申请号：US728495
申请日：1996-10-09
申请人： Ching-Fa Yeh , Jyh-Nan Jeng
发明人： Ching-Fa Yeh , Jyh-Nan Jeng
IPC分类号： H01L21/336 , H01L27/11 , H01L29/786 , H01L21/265
CPC分类号： H01L29/78696 , H01L27/1108 , H01L29/66765 , H01L29/78678
摘要： A polysilicon transistor having a buried-gate structure is fabricated by a method involving a liquid phase deposition which is used for depositing selectively a silicon dioxide layer on a polysilicon layer, but not on a photoresist layer. The silicon dioxide liquid phase deposition is brought about by using an aqueous hydrofluorosilicic acid (H.sub.2 SiF.sub.6) solution supersaturated with silicon dioxide. Upon completion of the stripping of the photoresist layer, the selectively-deposited silicon dioxide layer is used as a mask to perform the source/drain ion implant.
摘要翻译：具有掩埋栅结构的多晶硅晶体管通过包括液相沉积的方法制造，该方法用于在多晶硅层上但不在光致抗蚀剂层上选择性地沉积二氧化硅层。通过使用二氧化硅过饱和的氢氟硅酸（H 2 SiF 6）水溶液进行二氧化硅液相沉积。在光致抗蚀剂层的剥离完成时，选择沉积的二氧化硅层用作掩模来执行源/漏离子注入。

5. 发明授权

US5776835A Method of making a grooved gate structure of semiconductor device 失效
标题翻译：制造半导体器件的沟槽栅极结构的方法
公开(公告)号：US5776835A
公开(公告)日：1998-07-07
申请号：US599135
申请日：1996-02-09
申请人： Ching-Fa Yeh , Jwinn Lein Su
发明人： Ching-Fa Yeh , Jwinn Lein Su
IPC分类号： H01L21/311 , H01L21/314 , H01L21/316 , H01L21/336 , H01L21/60 , H01L29/49 , H01L21/00
CPC分类号： H01L21/76897 , H01L21/31111 , H01L21/316 , H01L29/4925 , H01L29/665 , H01L29/66515 , H01L29/66545 , H01L29/66575
摘要： A method is capable of providing a semiconductor device with a gate having thereon a thicker silicide or metal layer and further having a lower interconnect resistance. The method is further capable of providing the semiconductor device with a polysilicon gate having a recessed tungsten structure for prevention of short circuit between the gate and the drain or the source. For forming a grooved gate structure, a photo-resist is formed on the polysilicon gate before growing on the entire surface of the silicon substrate a silicon dioxide layer. The silicon dioxide layer and the thin gate oxidation layer on drain/source are etched vertically by a reactive ion etching until the photo-resist and the silicon surface of drain/source are exposed. A plurality of spacers are thus formed on the side walls of the photo-resist/polysilicon gate. Upon stripping the photo-resist, the grooved gate structure is formed on the semiconductor device.
摘要翻译：一种方法能够提供具有栅极的半导体器件，其上具有较厚的硅化物或金属层，并且还具有较低的互连电阻。该方法还能够为半导体器件提供具有凹陷钨结构的多晶硅栅极，以防止栅极和漏极或源极之间的短路。为了形成沟槽栅极结构，在硅衬底的整个表面上生长二氧化硅层之前，在多晶硅栅极上形成光致抗蚀剂。通过反应离子蚀刻垂直蚀刻漏极/源极上的二氧化硅层和薄栅氧化层，直到暴露出光致抗蚀剂和漏极/源极的硅表面。因此，在光致抗蚀剂/多晶硅栅极的侧壁上形成多个间隔物。在剥离光刻胶时，在半导体器件上形成带槽栅极结构。

6. 发明授权

US4961101A Semiconductor MOSFET device with offset regions 失效
标题翻译：具有偏移区域的半导体MOSFET器件
公开(公告)号：US4961101A
公开(公告)日：1990-10-02
申请号：US183847
申请日：1988-04-20
申请人： Ching Fa Yeh , Yuji Yatsuda
发明人： Ching Fa Yeh , Yuji Yatsuda
IPC分类号： H01L27/088 , H01L29/06 , H01L29/08 , H01L29/78
CPC分类号： H01L29/0847 , H01L27/088 , H01L29/0692 , H01L29/7835
摘要： In a semiconductor device comprising a plurality of planar high-voltage insulated-gate field-effect transistors in which offset regions are provided in portions of the semiconductor substrate near the junctions of adjacent drain regions and near the substrate surface additional, low impurity concentration offset regions are formed in the semiconductor substrate in such a manner that each low impurity concentration offset region is coupled to a source region and is located between the drain regions of the field-effect transistors adjacent to each other and near the semiconductor surface, whereby reduction of the "on resistance" is achieved without affecting the FET sustaining voltage.
摘要翻译：在包括多个平面高压绝缘栅场效应晶体管的半导体器件中，其中偏移区域设置在半导体衬底的靠近相邻漏极区域的接合部附近并且在衬底表面附近的附加的低杂质浓度偏移区域以这样的方式形成在半导体衬底中，使得每个低杂质浓度偏移区域耦合到源极区域并且位于彼此相邻并且靠近半导体表面的场效应晶体管的漏极区域之间，由此减少实现“导通电阻”而不影响FET的维持电压。

7. 发明授权

US07115449B2 Method for fabrication of polycrystalline silicon thin film transistors 有权
标题翻译：多晶硅薄膜晶体管的制造方法
公开(公告)号：US07115449B2
公开(公告)日：2006-10-03
申请号：US10867660
申请日：2004-06-16
申请人： Ching-Fa Yeh , Tien-Fu Chen , Jen-Chung Lou
发明人： Ching-Fa Yeh , Tien-Fu Chen , Jen-Chung Lou
IPC分类号： H01L21/00
CPC分类号： H01L21/02683 , H01L21/02532 , H01L21/02595 , H01L21/02686 , H01L21/2026 , H01L27/1281 , H01L27/1296 , H01L29/66757
摘要： The present invention provides a method for fabrication of polycrystalline silicon thin film transistors, which forms a silicon spacer on the sidewall of the active layer of a thin film transistor (TFT) by way of anisotropic plasma etching in a single direction. The silicon spacer provides a mechanism for laser recrystallization on the sidewall to prevent the active layer from shrinkage or shelling-off after the laser recrystallization. According to the present invention, large grains can be formed in the channel without additional mask during production. By doing so, the characteristics of the components are enhanced; the uniformity is improved; and, the production cost is lowered. Therefore, this technique will play an important role in the fields of low temperature polycrystalline silicon thin film transistor (LTPS-TFT).
摘要翻译：本发明提供一种多晶硅薄膜晶体管的制造方法，其通过在单一方向上的各向异性等离子体蚀刻在薄膜晶体管（TFT）的有源层的侧壁上形成硅间隔物。硅衬垫提供了在侧壁上激光再结晶的机制，以防止活性层在激光再结晶后收缩或脱落。根据本发明，在生产中可以在通道中形成大的颗粒而不需要额外的掩模。通过这样做，组件的特性得到提高; 均匀性提高; 生产成本降低。因此，这种技术将在低温多晶硅薄膜晶体管（LTPS-TFT）领域发挥重要作用。

8. 发明授权

US06774461B2 Method of reducing thick film stress of spin-on dielectric and the resulting sandwich dielectric structure 有权
标题翻译：降低旋涂电介质厚膜应力的方法和所得夹心电介质结构
公开(公告)号：US06774461B2
公开(公告)日：2004-08-10
申请号：US10075293
申请日：2002-02-15
申请人： Ching-Fa Yeh , Yueh-Chuan Lee , Chih-Chuan Hsu , Kwo-Hau Wu , Shuo-Cheng Wang
发明人： Ching-Fa Yeh , Yueh-Chuan Lee , Chih-Chuan Hsu , Kwo-Hau Wu , Shuo-Cheng Wang
IPC分类号： H01L2358
CPC分类号： H01L21/76801 , H01L21/02131 , H01L21/02137 , H01L21/022 , H01L21/02282 , H01L21/02332 , H01L21/0234 , H01L21/3122 , H01L21/316 , H01L21/31629 , H01L21/76826 , H01L21/76828 , H01L21/76829 , Y10T428/265
摘要： The present invention provides a technique to reduce a stress of thick spin-on dielectric layer by forming a sandwich dielectric structure, wherein a first dielectric layer is formed on a substrate by spin coating, a liquid phase deposited (LPD) silica layer is formed the first dielectric layer, and a second dielectric layer is formed on the LPD silica layer by spin coating. The LPD silica layer can be further subjected to a nitrogen plasma treatment to enhance its thermal stability and anti-water penetration ability.
摘要翻译：本发明提供一种通过形成夹层电介质结构来减小厚的自旋电介质层的应力的技术，其中通过旋涂形成在基板上的第一介电层，形成液相沉积（LPD）二氧化硅层第一电介质层，并且通过旋涂在LPD二氧化硅层上形成第二电介质层。可以进一步对LPD二氧化硅层进行氮等离子体处理，以提高其热稳定性和抗水渗透能力。

9. 发明授权

US4818719A Method of manufacturing an integrated CMOS of ordinary logic circuit and of high voltage MOS circuit 失效
标题翻译：制造普通逻辑电路和高压MOS电路的集成CMOS的方法
公开(公告)号：US4818719A
公开(公告)日：1989-04-04
申请号：US74059
申请日：1987-07-16
申请人： Ching-Fa Yeh , Yasunao Misawa , Yuji Yatsuda
发明人： Ching-Fa Yeh , Yasunao Misawa , Yuji Yatsuda
IPC分类号： H01L27/08 , H01L21/8238 , H01L27/088 , H01L29/78 , H01L21/265
CPC分类号： H01L21/8238 , H01L27/088
摘要： A method of manufacturing a semiconductor device having a high voltage CMOS unit for an ordinary logic operation and a MOS unit which are provided in a single semiconductor substrate of a first conduction type. The method includes the steps of performing an element region making process for making a well of a second conduction type in the substrate, performing a process for providing field-effect transistors having channels of mutually different conduction types in the substrate and the well, and then performing a process for providing electrode wiring layers. Finally, a process is performed for providing a first impurity region having a particular conduction type and serving as a channel stopper of the CMOS unit and a second impurity region having the conduction type of the first impurity region and serving as an offset low-resistance layer of the high voltage MOS unit.
摘要翻译：一种制造具有用于普通逻辑运算的高电压CMOS单元和设置在第一导电类型的单个半导体衬底中的MOS单元的半导体器件的方法。该方法包括以下步骤：在衬底中进行用于制造第二导电类型的阱的元件区域制造工艺，在衬底和阱中执行提供具有相互不同导电类型的沟道的场效应晶体管的工艺，然后执行用于提供电极布线层的工艺。最后，进行用于提供具有特定导电类型并用作CMOS单元的沟道阻挡的第一杂质区和具有第一杂质区的导电类型并用作偏移低电阻层的第二杂质区的高压MOS单元。

10. 发明授权

US06251753B1 Method of sidewall capping for degradation-free damascene trenches of low dielectric constant dielectric by selective liquid-phase deposition 有权
标题翻译：通过选择性液相沉积对低介电常数电介质的无降解镶嵌沟槽进行侧壁封盖的方法
公开(公告)号：US06251753B1
公开(公告)日：2001-06-26
申请号：US09447715
申请日：1999-11-23
申请人： Ching-Fa Yeh , Yueh-Chuan Lee , Yuh-Ching Su , Kwo-Hau Wu
发明人： Ching-Fa Yeh , Yueh-Chuan Lee , Yuh-Ching Su , Kwo-Hau Wu
IPC分类号： H01L2176
CPC分类号： H01L21/02137 , H01L21/02282 , H01L21/02362 , H01L21/3122 , H01L21/76814 , H01L21/76826 , H01L21/76828 , H01L21/76829 , H01L21/76831
摘要： A low dielectric constant (k) material, such as methylsilsesquioxane (MSQ), used as an interlevel dielectric is expected to reduce the parasitic capacitance in integrated circuit. However, MSQ film can be easily degraded during resist ashing after the film is etched with the damascene trenches being created. The present invention discloses an innovative sidewall capping technology to solve the degradation issue. Prior to resist ashing, a high-quality, low-k oxide film is selectively deposited onto the sidewalls of MSQ trenches using selective liquid-phase deposition. Experimental results demonstrate that the capping oxide can effectively protect the sidewalls of MSQ trenches from ashing-induced degradation.
摘要翻译：用作层间电介质的低介电常数（k）材料，如甲基倍半硅氧烷（MSQ），有望降低集成电路中的寄生电容。然而，在蚀刻形成镶嵌的沟槽之后的抗蚀剂灰化过程中，MSQ膜可以容易地劣化。本发明公开了一种创新的侧壁封盖技术来解决退化问题。在抗蚀灰化之前，使用选择性液相沉积将高质量，低k氧化物膜选择性地沉积在MSQ沟槽的侧壁上。实验结果表明，覆盖氧化物可以有效地保护MSQ沟槽的侧壁免受灰分诱导的退化。

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