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1. 发明申请

US20130009143A1 PHOTO SENSOR AND METHOD OF FABRICATING THE SAME 审中-公开
标题翻译：照相传感器及其制造方法
公开(公告)号：US20130009143A1
公开(公告)日：2013-01-10
申请号：US13253656
申请日：2011-10-05
申请人： Chih Chen , Chien-Min Liu , Yuan-Chieh Tseng
发明人： Chih Chen , Chien-Min Liu , Yuan-Chieh Tseng
IPC分类号： H01L31/0264 , H01L31/18
CPC分类号： H01L31/035227 , H01L31/108
摘要： A photo sensor and a method of fabricating the same are disclosed, the photo sensor of the present invention has ultra-high Schottky junction area per unit volume, and the photo sensor comprises: a first conductive layer; plural metallic nanowires, in which one end of each metallic nanowire connects with the first conductive layer and is covered with a semiconductive layer having a width of 1 nm to 20 nm; and a second conductive layer locating opposite to the first conductive layer, whereby the plural metallic nanowires locate between the first conductive layer and the second conductive layer, and the semiconductive layer contacts with the second conductive layer, wherein the photo sensor of the present invention is used to detect ultra violet (UV) light with a wavelength of 10 nm-400 nm.
摘要翻译：公开了一种光传感器及其制造方法，本发明的光传感器具有每单位体积的超高肖特基结面积，光传感器包括：第一导电层; 多个金属纳米线，其中每个金属纳米线的一端与第一导电层连接并且被宽度为1nm至20nm的半导体层覆盖; 以及与所述第一导电层相对定位的第二导电层，由此所述多个金属纳米线位于所述第一导电层和所述第二导电层之间，并且所述半导体层与所述第二导电层接触，其中本发明的光电传感器为用于检测波长为10nm-400nm的紫外（UV）光。

2. 发明申请

US20110042782A1 ON-CHIP INDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：片上电感结构及其制造方法
公开(公告)号：US20110042782A1
公开(公告)日：2011-02-24
申请号：US12607433
申请日：2009-10-28
申请人： TZU-YUAN CHAO , MING-CHIEH HSU , YU-TING CHENG , CHIH CHEN , CHIEN-MIN LIU
发明人： TZU-YUAN CHAO , MING-CHIEH HSU , YU-TING CHENG , CHIH CHEN , CHIEN-MIN LIU
IPC分类号： H01L29/86 , H01L21/02
CPC分类号： H01L28/10
摘要： The present invention relates to a an on-chip inductor structure and a method for manufacturing the same. The an on-chip inductor structure according to the present invention comprises a substrate, a porous layer, a plurality of conductors, and an inductor. The porous layer is disposed on the substrate and has a plurality of voids; each of the plurality of conductors is disposed in the plurality of voids, respectively; and the inductor is disposed on the porous layer. Because the plurality of conductors is used as the core of the inductor, the inductance is increased effectively and the area of the an on-chip inductor is reduced. Besides the manufacturing method according to the present invention is simple and compatible with the current CMOS process, the manufacturing cost can be lowered.
摘要翻译：片上电感器结构及其制造方法技术领域本发明涉及片上电感结构及其制造方法。根据本发明的片上电感器结构包括衬底，多孔层，多个导体和电感器。多孔层设置在基板上并具有多个空隙; 多个导体中的每一个分别设置在多个空隙中; 并且电感器设置在多孔层上。由于使用多个导体作为电感的核心，所以电感被有效地增加并且片上电感器的面积减小。此外，根据本发明的制造方法简单且兼容于目前的CMOS工艺，可以降低制造成本。

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