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1. 发明授权

US07519774B2 Data processor having a memory control unit with cache memory 失效
标题翻译：数据处理器具有具有高速缓冲存储器的存储器控制单元
公开(公告)号：US07519774B2
公开(公告)日：2009-04-14
申请号：US11130217
申请日：2005-05-17
申请人： Fumie Katsuki , Takanobu Naruse , Chiaki Fujii
发明人： Fumie Katsuki , Takanobu Naruse , Chiaki Fujii
IPC分类号： G06F13/00
CPC分类号： G06F12/0875 , G06F13/1678
摘要： The data processor enhances the bus throughput or data throughput of an external memory, when there are frequent continuous reads with a smaller data size than the data bus width of the external memory. The data processor includes a memory control unit being capable of controlling in response to a clock an external memory having plural banks that are individually independently controllable, plural buses connected to the memory control unit, and circuit modules capable of commanding memory accesses, which are provided in correspondence with each of the buses. The memory control unit contains bank caches each corresponding to the banks of the external memory. Thereby, the data processor enhances the bus throughput or data throughput of the external memory, since the data processor stores the data read out from the external memory temporarily in the bank caches and to use the stored data without invalidating them, when performing a continuous data read with a smaller data size than the data bus width of the external memory.
摘要翻译：当存在与外部存储器的数据总线宽度相比更小的数据大小的频繁连续读取时，数据处理器增强了外部存储器的总线吞吐量或数据吞吐量。该数据处理器包括一个存储器控制单元，该存储器控制单元能够响应于时钟来控制具有独立可独立控制的多个存储体的外部存储器，连接到存储器控制单元的多个总线以及能够命令存储器访问的电路模块与每条巴士对应。存储器控制单元包含每个对应于外部存储器的存储体的存储体缓存。因此，数据处理器增强了外部存储器的总线吞吐量或数据吞吐量，因为数据处理器将从外部存储器中读出的数据临时存储在存储体高速缓存中并且在执行连续数据时使用存储的数据而不使其消失以比外部存储器的数据总线宽度更小的数据大小读取。

2. 发明授权

US4350361A Load carrying platform for a bicycle 失效
标题翻译：自行车负载平台
公开(公告)号：US4350361A
公开(公告)日：1982-09-21
申请号：US185636
申请日：1980-09-09
申请人： Chiaki Fujii
发明人： Chiaki Fujii
IPC分类号： B62J7/04 , B62J7/06
CPC分类号： B62J7/04 , B62J7/06
摘要： A load carrying platform for a bicycle comprises a load carrying platform body for placing a load thereon, leg members for securing the platform body to a bicycle frame and mounting members. The load carrying platform body comprises rigid plate-like transverse members, outer frame members and inner frame members, the leg members having upper ends connected to the transverse members. The upper surface of the transverse member is positioned at a level higher than the outer frame member or inner frame member, and accordingly, the weight of the load placed on the load carrying platform body is applied to the leg members through the transverse members.
摘要翻译：用于自行车的承载平台包括用于在其上放置负载的承载平台本体，用于将平台主体固定到自行车车架和安装构件的腿部构件。负载平台体包括刚性板状横向构件，外框架构件和内框架构件，腿构件具有连接到横向构件的上端。横向构件的上表面位于比外框架构件或内框架构件高的位置上，因此通过横向构件将承载平台体上的载荷的重量施加到腿构件。

3. 发明申请

US20110305060A1 WIRING SUBSTRATE IN WHICH EQUAL-LENGTH WIRES ARE FORMED 有权
标题翻译：形成等长线的配线基板
公开(公告)号：US20110305060A1
公开(公告)日：2011-12-15
申请号：US13156049
申请日：2011-06-08
申请人： Takashi ICHIMURA , Takanobu NARUSE , Chiaki FUJII
发明人： Takashi ICHIMURA , Takanobu NARUSE , Chiaki FUJII
IPC分类号： G11C5/06
CPC分类号： G11C5/063
摘要： In a wiring substrate, a double data rate (DDR) memory and a memory controller controlling the DDR memory are mounted. Further, in the wiring substrate, plural equal-length wires connecting the DDR memory and the memory controller are formed. The plural equal-length wires include a differential transmission line, such as a clock wire transmitting a clock signal, which is connected via a common mode choke coil. The differential transmission line may have a wire length shorter than a wire length of another equal-length wire, by a wire length corresponding to delay time of a transmission signal due to the common mode choke coil.
摘要翻译：在布线基板中，安装双倍数据速率（DDR）存储器和控制DDR存储器的存储器控制器。此外，在布线基板中，形成连接DDR存储器和存储器控制器的多条等长线。多条等长导线包括差分传输线，例如传输时钟信号的时钟线，其通过共模扼流线圈连接。差分传输线可以具有比另一等长线的线长短的导线长度，其对应于由于共模扼流线圈引起的发送信号的延迟时间的线长度。

4. 发明授权

US08032715B2 Data processor 失效
标题翻译：数据处理器
公开(公告)号：US08032715B2
公开(公告)日：2011-10-04
申请号：US12848777
申请日：2010-08-02
申请人： Fumie Katsuki , Takanobu Naruse , Chiaki Fujii
发明人： Fumie Katsuki , Takanobu Naruse , Chiaki Fujii
IPC分类号： G06F13/00
CPC分类号： G06F12/0875 , G06F13/1678
摘要： The data processor enhances the bus throughput or data throughput of an external memory, when there are frequent continuous reads with a smaller data size than the data bus width of the external memory. The data processor includes a memory control unit being capable of controlling in response to a clock an external memory having plural banks that are individually independently controllable, plural buses connected to the memory control unit, and circuit modules capable of commanding memory accesses, which are provided in correspondence with each of the buses. The memory control unit contains bank caches each corresponding to the banks of the external memory. Thereby, the data processor enhances the bus throughput or data throughput of the external memory, since the data processor stores the data read out from the external memory temporarily in the bank caches and to use the stored data without invalidating them, when performing a continuous data read with a smaller data size than the data bus width of the external memory.
摘要翻译：当存在与外部存储器的数据总线宽度相比更小的数据大小的频繁连续读取时，数据处理器增强了外部存储器的总线吞吐量或数据吞吐量。该数据处理器包括一个存储器控制单元，该存储器控制单元能够响应时钟控制具有独立可独立控制的多个存储体的外部存储器，连接到存储器控制单元的多个总线以及能够命令存储器访问的电路模块与每条巴士对应。存储器控制单元包含每个对应于外部存储器的存储体的存储体缓存。因此，数据处理器增强了外部存储器的总线吞吐量或数据吞吐量，因为数据处理器将从外部存储器中读出的数据临时存储在存储体高速缓存中并且在执行连续数据时使用存储的数据而不使其消失以比外部存储器的数据总线宽度更小的数据大小读取。

5. 发明申请

US20100318732A1 DATA PROCESSOR 失效
标题翻译：数据处理器
公开(公告)号：US20100318732A1
公开(公告)日：2010-12-16
申请号：US12848777
申请日：2010-08-02
申请人： Fumie Katsuki , Takanobu Naruse , Chiaki Fujii
发明人： Fumie Katsuki , Takanobu Naruse , Chiaki Fujii
IPC分类号： G06F12/06
CPC分类号： G06F12/0875 , G06F13/1678
摘要： The data processor enhances the bus throughput or data throughput of an external memory, when there are frequent continuous reads with a smaller data size than the data bus width of the external memory. The data processor includes a memory control unit being capable of controlling in response to a clock an external memory having plural banks that are individually independently controllable, plural buses connected to the memory control unit, and circuit modules capable of commanding memory accesses, which are provided in correspondence with each of the buses. The memory control unit contains bank caches each corresponding to the banks of the external memory. Thereby, the data processor enhances the bus throughput or data throughput of the external memory, since the data processor stores the data read out from the external memory temporarily in the bank caches and to use the stored data without invalidating them, when performing a continuous data read with a smaller data size than the data bus width of the external memory.
摘要翻译：当存在与外部存储器的数据总线宽度相比更小的数据大小的频繁连续读取时，数据处理器增强了外部存储器的总线吞吐量或数据吞吐量。该数据处理器包括一个存储器控制单元，该存储器控制单元能够响应于时钟来控制具有独立可独立控制的多个存储体的外部存储器，连接到存储器控制单元的多个总线以及能够命令存储器访问的电路模块与每条巴士对应。存储器控制单元包含每个对应于外部存储器的存储体的存储体缓存。因此，数据处理器增强了外部存储器的总线吞吐量或数据吞吐量，因为数据处理器将从外部存储器中读出的数据临时存储在存储体高速缓存中并且在执行连续数据时使用存储的数据而不使其消失以比外部存储器的数据总线宽度更小的数据大小读取。

6. 发明授权

US06573925B2 Optical printer module 失效
标题翻译：光学打印机模块
公开(公告)号：US06573925B2
公开(公告)日：2003-06-03
申请号：US09812903
申请日：2001-03-21
申请人： Hiroshi Ohmura , Ko Aosaki , Hiroyuki Uchiyama , Seiji Takada , Hiroshi Soma , Chiaki Fujii , Seimei Ushiro
发明人： Hiroshi Ohmura , Ko Aosaki , Hiroyuki Uchiyama , Seiji Takada , Hiroshi Soma , Chiaki Fujii , Seimei Ushiro
IPC分类号： B41J2435
CPC分类号： G03B17/52
摘要： An optical printer module has a film pack compartment that stores a film pack which stores an instant print film in a frame composed of a main frame, a subframe and a cover. The frame contains a claw mechanism and a spread mechanism that includes a pair of spread rollers. The claw mechanism feeds the instant print film out of the film pack while the instant print film is being exposed, and the spread rollers pinch the exposed instant print film fed out of the film pack by the claw mechanism to develop the exposed instant print film and feed the developed instant print film from the optical printer module. The whole surface of the frame shades the film, except for an opening for the film pack.
摘要翻译：光学打印机模块具有胶片盒室，该胶片盒存储在由主框架，子框架和盖子构成的框架中存储即时印刷胶片的胶卷盒。框架包括爪机构和包括一对展开辊的展开机构。爪机构在即时印刷薄膜被曝光的同时将即时印刷薄膜送出薄膜包装，并且展开辊通过爪机构夹持从薄膜包装送出的曝光的即时印刷薄膜，以显影曝光的即时印刷薄膜，从光学打印机模块馈送显影的即时印刷胶片。除了薄膜包装的开口之外，框架的整个表面遮盖了胶片。

7. 发明授权

US08659927B2 Wiring substrate in which equal-length wires are formed 有权
标题翻译：形成等长导线的布线基板
公开(公告)号：US08659927B2
公开(公告)日：2014-02-25
申请号：US13156049
申请日：2011-06-08
申请人： Takashi Ichimura , Takanobu Naruse , Chiaki Fujii
发明人： Takashi Ichimura , Takanobu Naruse , Chiaki Fujii
IPC分类号： G11C5/06
CPC分类号： G11C5/063
摘要： In a wiring substrate, a double data rate (DDR) memory and a memory controller controlling the DDR memory are mounted. Further, in the wiring substrate, plural equal-length wires connecting the DDR memory and the memory controller are formed. The plural equal-length wires include a differential transmission line, such as a clock wire transmitting a clock signal, which is connected via a common mode choke coil. The differential transmission line may have a wire length shorter than a wire length of another equal-length wire, by a wire length corresponding to delay time of a transmission signal due to the common mode choke coil.
摘要翻译：在布线基板中，安装双倍数据速率（DDR）存储器和控制DDR存储器的存储器控制器。此外，在布线基板中，形成连接DDR存储器和存储器控制器的多条等长线。多条等长导线包括差分传输线，例如传输时钟信号的时钟线，其通过共模扼流线圈连接。差分传输线可以具有比另一等长线的线长短的导线长度，其对应于由于共模扼流线圈引起的发送信号的延迟时间的线长度。

8. 发明授权

US07783827B2 Data processor having a memory controller with cache memory 失效
标题翻译：具有具有高速缓冲存储器的存储器控制器的数据处理器
公开(公告)号：US07783827B2
公开(公告)日：2010-08-24
申请号：US12410437
申请日：2009-03-24
申请人： Fumie Katsuki , Takanobu Naruse , Chiaki Fujii
发明人： Fumie Katsuki , Takanobu Naruse , Chiaki Fujii
IPC分类号： G06F13/00
CPC分类号： G06F12/0875 , G06F13/1678
摘要： The data processor enhances the bus throughput or data throughput of an external memory, when there are frequent continuous reads with a smaller data size than the data bus width of the external memory. The data processor includes a memory control unit being capable of controlling in response to a clock an external memory having plural banks that are individually independently controllable, plural buses connected to the memory control unit, and circuit modules capable of commanding memory accesses, which are provided in correspondence with each of the buses. The memory control unit contains bank caches each corresponding to the banks of the external memory. Thereby, the data processor enhances the bus throughput or data throughput of the external memory, since the data processor stores the data read out from the external memory temporarily in the bank caches and to use the stored data without invalidating them, when performing a continuous data read with a smaller data size than the data bus width of the external memory.
摘要翻译：当存在与外部存储器的数据总线宽度相比更小的数据大小的频繁连续读取时，数据处理器增强了外部存储器的总线吞吐量或数据吞吐量。该数据处理器包括一个存储器控制单元，该存储器控制单元能够响应于时钟来控制具有独立可独立控制的多个存储体的外部存储器，连接到存储器控制单元的多个总线以及能够命令存储器访问的电路模块与每条巴士对应。存储器控制单元包含每个对应于外部存储器的存储体的存储体缓存。因此，数据处理器增强了外部存储器的总线吞吐量或数据吞吐量，因为数据处理器将从外部存储器中读出的数据临时存储在存储体高速缓存中并且在执行连续数据时使用存储的数据而不使其消失以比外部存储器的数据总线宽度更小的数据大小读取。

9. 发明申请

US20090182943A1 DATA PROCESSOR 失效
标题翻译：数据处理器
公开(公告)号：US20090182943A1
公开(公告)日：2009-07-16
申请号：US12410437
申请日：2009-03-24
申请人： FUMIE KATSUKI , Takanobu NARUSE , Chiaki FUJII
发明人： FUMIE KATSUKI , Takanobu NARUSE , Chiaki FUJII
IPC分类号： G06F12/08
CPC分类号： G06F12/0875 , G06F13/1678
摘要： The data processor enhances the bus throughput or data throughput of an external memory, when there are frequent continuous reads with a smaller data size than the data bus width of the external memory. The data processor includes a memory control unit being capable of controlling in response to a clock an external memory having plural banks that are individually independently controllable, plural buses connected to the memory control unit, and circuit modules capable of commanding memory accesses, which are provided in correspondence with each of the buses. The memory control unit contains bank caches each corresponding to the banks of the external memory. Thereby, the data processor enhances the bus throughput or data throughput of the external memory, since the data processor stores the data read out from the external memory temporarily in the bank caches and to use the stored data without invalidating them, when performing a continuous data read with a smaller data size than the data bus width of the external memory.
摘要翻译：当存在与外部存储器的数据总线宽度相比更小的数据大小的频繁连续读取时，数据处理器增强了外部存储器的总线吞吐量或数据吞吐量。该数据处理器包括一个存储器控制单元，该存储器控制单元能够响应于时钟来控制具有独立可独立控制的多个存储体的外部存储器，连接到存储器控制单元的多个总线以及能够命令存储器访问的电路模块与每条巴士对应。存储器控制单元包含每个对应于外部存储器的存储体的存储体缓存。因此，数据处理器增强了外部存储器的总线吞吐量或数据吞吐量，因为数据处理器将从外部存储器中读出的数据临时存储在存储体高速缓存中并且在执行连续数据时使用存储的数据而不使其消失以比外部存储器的数据总线宽度更小的数据大小读取。

10. 发明授权

US07542783B2 Portable communication terminal 失效
标题翻译：便携式通讯终端
公开(公告)号：US07542783B2
公开(公告)日：2009-06-02
申请号：US10815802
申请日：2004-04-02
申请人： Hiroshi Ohmura , Ko Aosaki , Hiroyuki Uchiyama , Seiji Takada , Hiroshi Soma , Chiaki Fujii , Seimei Ushiro
发明人： Hiroshi Ohmura , Ko Aosaki , Hiroyuki Uchiyama , Seiji Takada , Hiroshi Soma , Chiaki Fujii , Seimei Ushiro
IPC分类号： H04B1/38
CPC分类号： H04M1/21 , H04M1/0202 , H04M1/0254 , H04M1/22 , H04M1/72527 , H04M1/7253 , H04M2250/16 , H04W52/027 , Y02D70/144
摘要： A cellular phone has a black-and-white LCD that displays characters and communication information and a color LCD that displays an image. The image and the characters are displayed on the separate LCDs. Thus, the characters are not superimposed on the image, and they are easy to see. When the image is not needed (the user is not using the phone or the user is talking on the phone), only the black-and-white LCD displays the characters and the color LCD is turned off to save energy.
摘要翻译：手机具有显示字符和通信信息的黑白LCD以及显示图像的彩色LCD。图像和字符显示在单独的LCD上。因此，字符不叠加在图像上，它们很容易看到。当不需要图像（用户不使用手机或用户正在通话时），只有黑白液晶显示器才能显示字符，彩色液晶显示屏已关闭以节省能源。

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