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1. 发明授权

US08038735B2 Deep dyeing process of polyamide and polyolefin 有权
标题翻译：聚酰胺和聚烯烃的深染工艺
公开(公告)号：US08038735B2
公开(公告)日：2011-10-18
申请号：US12550558
申请日：2009-08-31
申请人： Jen-Taut Yeh , Kan-Nan Chen , Chi-Hui Tsou , Jing-Wen Tang
发明人： Jen-Taut Yeh , Kan-Nan Chen , Chi-Hui Tsou , Jing-Wen Tang
IPC分类号： D06P3/06 , D06P3/10
CPC分类号： D01F6/90 , D01F1/10 , D01F6/04 , D01F6/60 , D06P1/445 , D06P3/241 , D06P3/248 , D06P3/791 , D06P3/798 , Y10S8/924
摘要： In a deep dyeing process of a polyamide (PA) including Nylon 4, Nylon 6, Nylon 46, Nylon 66, Nylon 7, Nylon 8, Nylon 9, Nylon 610, Nylon 1010, Nylon 11, Nylon 12, Nylon 13, Nylon 612, Nylon 9T, Nylon 13, MC Nylon, Nylon MXD6, and all polyamide derivatives, and a polyolefin (PO) including ethylene copolymer, propylene copolymer and their derivatives, a compatibilizer precursor is used for modifying the polyamide and polyolefin of an amino, hydroxyl or epoxy group containing chemical, and then a reactive dye and/or an acid dye is used for dyeing the polyamide and polyolefin, so that the dyed polyamide and polyolefin have excellent dye fastness, light fastness, rubbing fastness, washing fastness and low-temperature dyeability to overcome the shortcomings of conventional nylon fibers including a poor dyeing effect, a non-level dyeing quality, a high dyeing temperature (100° C. to 120° C.) and a high cost.
摘要翻译：在包括尼龙4，尼龙6，尼龙46，尼龙66，尼龙7，尼龙8，尼龙9，尼龙610，尼龙1010，尼龙11，尼龙12，尼龙13，尼龙612的聚酰胺（PA）的深度染色过程中，尼龙9T，尼龙13，MC尼龙，尼龙MXD6和所有聚酰胺衍生物，以及包含乙烯共聚物，丙烯共聚物及其衍生物的聚烯烃（PO），相容剂前体用于改性聚酰胺和聚烯烃的氨基，羟基或含环氧基的化学物质，然后使用活性染料和/或酸性染料染色聚酰胺和聚烯烃，使得染色的聚酰胺和聚烯烃具有优异的耐色牢度，耐光性，耐摩擦牢度，耐洗牢度和低温可染性能克服常规尼龙纤维的缺点，包括染色效果差，染色质量差，染色温度高（100〜120℃），成本高。

2. 发明申请

US20110047719A1 Deep Dyeing Process of Polyamide and Polyolefin 有权
标题翻译：聚酰胺和聚烯烃的深染工艺
公开(公告)号：US20110047719A1
公开(公告)日：2011-03-03
申请号：US12550558
申请日：2009-08-31
申请人： Jen-Taut YEH , Kan-Nan Chen , Chi-Hui Tsou , Jing-Wen Tang
发明人： Jen-Taut YEH , Kan-Nan Chen , Chi-Hui Tsou , Jing-Wen Tang
IPC分类号： D06P7/00
CPC分类号： D01F6/90 , D01F1/10 , D01F6/04 , D01F6/60 , D06P1/445 , D06P3/241 , D06P3/248 , D06P3/791 , D06P3/798 , Y10S8/924
摘要： In a deep dyeing process of a polyamide (PA) including Nylon 4, Nylon 6, Nylon 46, Nylon 66, Nylon 7, Nylon 8, Nylon 9, Nylon 610, Nylon 1010, Nylon 11, Nylon 12, Nylon 13, Nylon 612, Nylon 9T, Nylon 13, MC Nylon, Nylon MXD6, and all polyamide derivatives, and a polyolefin (PO) including ethylene copolymer, propylene copolymer and their derivatives, a compatibilizer precursor is used for modifying the polyamide and polyolefin of an amino, hydroxyl or epoxy group containing chemical, and then a reactive dye and/or an acid dye is used for dyeing the polyamide and polyolefin, so that the dyed polyamide and polyolefin have excellent dye fastness, light fastness, rubbing fastness, washing fastness and low-temperature dyeability to overcome the shortcomings of conventional nylon fibers including a poor dyeing effect, a non-level dyeing quality, a high dyeing temperature (100° C. to 120° C.) and a high cost.
摘要翻译：在包括尼龙4，尼龙6，尼龙46，尼龙66，尼龙7，尼龙8，尼龙9，尼龙610，尼龙1010，尼龙11，尼龙12，尼龙13，尼龙612的聚酰胺（PA）的深度染色过程中，尼龙9T，尼龙13，MC尼龙，尼龙MXD6和所有聚酰胺衍生物，以及包含乙烯共聚物，丙烯共聚物及其衍生物的聚烯烃（PO），相容剂前体用于改性聚酰胺和聚烯烃的氨基，羟基或含环氧基的化学物质，然后使用活性染料和/或酸性染料染色聚酰胺和聚烯烃，使得染色的聚酰胺和聚烯烃具有优异的耐色牢度，耐光性，耐摩擦牢度，耐洗牢度和低温可染性能克服常规尼龙纤维的缺点，包括染色效果差，染色质量差，染色温度高（100〜120℃），成本高。

3. 发明申请

US20090296950A1 SIGNAL PROCESSING SYSTEM HAVING A PLURALITY OF HIGH-VOLTAGE FUNCTIONAL BLOCKS INTEGRATED INTO INTERFACE MODULE AND METHOD THEREOF 有权
标题翻译：信号处理系统具有集成在接口模块中的多个高电压功能块及其方法
公开(公告)号：US20090296950A1
公开(公告)日：2009-12-03
申请号：US12128607
申请日：2008-05-28
申请人： Sheng-Jui Huang , Yung-Yu Lin , Jen-Che Tsai , Tzueng-Yau Lin , Yau-Wai Wong , Chih-Horng Weng , Chi-Hui Wang
发明人： Sheng-Jui Huang , Yung-Yu Lin , Jen-Che Tsai , Tzueng-Yau Lin , Yau-Wai Wong , Chih-Horng Weng , Chi-Hui Wang
IPC分类号： H03F3/217 , H04R1/10
CPC分类号： H04R3/00 , H04R2420/01
摘要： A signal processing system and related method are disclosed. The signal processing system includes a signal processing module, powered by a low supply voltage, for processing signals; and an interface module, coupled to the signal processing module, powered by a high supply voltage, for outputting signals generated from the signal processing module; wherein the interface module comprises a plurality of high-voltage functional blocks integrated therein, and each of the functional blocks is configured to perform a predetermined interface functionality. In this way, the bill-of-material (BOM) cost can be reduced.
摘要翻译：公开了一种信号处理系统及相关方法。信号处理系统包括由低电源供电的信号处理模块，用于处理信号; 以及接口模块，其耦合到由高电源电压供电的所述信号处理模块，用于输出从所述信号处理模块产生的信号; 其中所述接口模块包括集成在其中的多个高压功能块，并且每个所述功能块被配置为执行预定的接口功能。通过这种方式，可以减少物料单（BOM）成本。

4. 发明授权

US07323743B2 Floating gate 有权
标题翻译：浮动门
公开(公告)号：US07323743B2
公开(公告)日：2008-01-29
申请号：US11603771
申请日：2006-11-22
申请人： Ying-Cheng Chuang , Chung-Lin Huang , Chi-Hui Lin
发明人： Ying-Cheng Chuang , Chung-Lin Huang , Chi-Hui Lin
IPC分类号： H01L29/788
CPC分类号： H01L27/11521 , H01L21/28273 , H01L29/42324 , H01L29/7881
摘要： A floating gate and fabrication method thereof. A semiconductor substrate is provided, on which an oxide layer, a first conducting layer, and a patterned hard mask layer having an opening are sequentially formed. A spacer is formed on the sidewall of the opening. A second conducting layer is formed on the hard mask layer. The second conducting layer is planarized to expose the surface of the patterned hard mask layer. The surface of the second conducting layer is oxidized to form an oxide layer. The patterned hard mask layer and the oxide layer and the first conducting layer underlying the patterned hard mask layer are removed.
摘要翻译：浮栅及其制造方法。提供了半导体衬底，其上依次形成有氧化物层，第一导电层和具有开口的图案化硬掩模层。间隔件形成在开口的侧壁上。在硬掩模层上形成第二导电层。将第二导电层平坦化以暴露图案化硬掩模层的表面。第二导电层的表面被氧化形成氧化物层。图案化的硬掩模层和氧化物层以及图案化的硬掩模层下面的第一导电层被去除。

5. 发明授权

US07135731B2 Vertical DRAM and fabrication method thereof 有权
标题翻译：垂直DRAM及其制造方法
公开(公告)号：US07135731B2
公开(公告)日：2006-11-14
申请号：US10707396
申请日：2003-12-10
申请人： Ching-Nan Hsiao , Ying-Cheng Chuang , Chi-Hui Lin
发明人： Ching-Nan Hsiao , Ying-Cheng Chuang , Chi-Hui Lin
IPC分类号： H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L27/10876 , H01L27/10841 , H01L27/10864 , H01L27/10885 , Y10S257/905 , Y10S257/906 , Y10S257/908
摘要： A vertical DRAM and fabrication method thereof. The vertical DRAM has a plurality of memory cells on a substrate, and each of the memory cells has a trench capacitor, a vertical transistor, and a source-isolation oxide layer in a deep trench. The main advantage of the present invention is to form an annular source diffusion and an annular drain diffusion of the vertical transistor around the sidewall of the deep trench. As a result, when a gate of the transistor is turned on, an annular gate channel is provided. The width of the gate channel of the present invention is therefore increased.
摘要翻译：垂直DRAM及其制造方法。垂直DRAM在衬底上具有多个存储单元，并且每个存储单元在深沟槽中具有沟槽电容器，垂直晶体管和源极隔离氧化物层。本发明的主要优点是在深沟槽的侧壁周围形成环形源极扩散和垂直晶体管的环形漏极扩散。结果，当晶体管的栅极导通时，提供环形栅极沟道。因此，本发明的栅极通道的宽度增加。

6. 发明授权

US07005701B2 Method for fabricating a vertical NROM cell 有权
标题翻译：制造垂直NROM电池的方法
公开(公告)号：US07005701B2
公开(公告)日：2006-02-28
申请号：US10318551
申请日：2002-12-13
申请人： Ching-Nan Hsiao , Chi-Hui Lin , Chung-Lin Huang , Ying-Cheng Chuang
发明人： Ching-Nan Hsiao , Chi-Hui Lin , Chung-Lin Huang , Ying-Cheng Chuang
IPC分类号： H01L29/76 , H01L39/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L27/11568 , H01L27/115
摘要： A method for fabricating a vertical nitride read-only memory (NROM) cell. A substrate having at least one trench is provided. A spacer is formed over the sidewall of the trench. Subsequently, ion implantation is performed on the substrate using the spacer as a mask to form doping areas as bit lines in the substrate near its surface and the bottom of the trench. Bit line oxides are formed over each of the doping areas. After the spacer is removed, a conformable insulating layer as gate dielectric is deposited on the sidewall of the trench and the surface of the bit line oxide. Finally, a conductive layer as a word line is deposited over the insulating layer and fills in the trench.
摘要翻译：一种用于制造垂直氮化物只读存储器（NROM）单元的方法。提供具有至少一个沟槽的衬底。间隔件形成在沟槽的侧壁上。随后，使用间隔物作为掩模在衬底上进行离子注入，以在沟槽的表面和底部附近的衬底中形成作为位线的掺杂区域。在每个掺杂区域上形成位线氧化物。在移除间隔物之后，在沟槽的侧壁和位线氧化物的表面上沉积作为栅极电介质的适形绝缘层。最后，作为字线的导电层沉积在绝缘层上并填充在沟槽中。

7. 发明授权

US06995061B2 Multi-bit stacked-type non-volatile memory and manufacture method thereof 有权
公开(公告)号：US06995061B2
公开(公告)日：2006-02-07
申请号：US10779607
申请日：2004-02-18
申请人： Ching-Nan Hsiao , Chi-Hui Lin , Ying-Cheng Chuang
发明人： Ching-Nan Hsiao , Chi-Hui Lin , Ying-Cheng Chuang
IPC分类号： H01L21/336
CPC分类号： H01L21/28273 , H01L29/66825 , H01L29/7887
摘要： The present invention discloses a multi-bit stacked-type non-volatile memory having a spacer-shaped floating gate and a manufacturing method thereof. The manufacturing method includes forming a patterned dielectric layer containing arsenic on a semiconductor substrate, wherein the patterned dielectric layer defines an opening as an active area. A dielectric spacer is formed on a side wall of the patterned dielectric layer and a gate dielectric layer is formed on the semiconductor substrate. A source/drain region is formed by thermal driving method making arsenic diffusion from the patterned dielectric layer into the semiconductor substrate. A spacer-shaped floating gate is formed on the side wall of the dielectric spacer and the gate dielectric layer. An interlayer dielectric layer is formed on the spacer-shaped floating gate. A control gate is formed on the interlayer dielectric layer and fills the opening of the active area.

8. 发明申请

US20060018633A1 Digital video storage system and related method of storing digital video data 审中-公开
标题翻译：数字视频存储系统及存储数字视频数据的相关方法
公开(公告)号：US20060018633A1
公开(公告)日：2006-01-26
申请号：US10710594
申请日：2004-07-22
申请人： Ching-Yu Tsai , Chi-Hui Huang
发明人： Ching-Yu Tsai , Chi-Hui Huang
IPC分类号： H04N5/781
CPC分类号： H04N5/765 , G11B20/10527 , G11B2020/10537 , G11B2020/10638 , G11B2020/10759
摘要： A digital video (DV) storage system comprises an interface module receiving an incoming signal and converting the incoming signal into an incoming bit-stream; a DV demuxer directly connected to the interface module for receiving the incoming bit-stream, wherein the DV demuxer de-multiplexes received blocks in the incoming bit-stream into at least video blocks being in video sections and audio blocks being in audio sections; and memory coupled to the DV demuxer for storing the video blocks and audio blocks. By directly connecting the interface module to the DV demuxer, and by not buffering the incoming bit-stream outside the interface module and the DV demuxer, the memory bandwidth requirement of the memory is greatly reduced, and the interface module and the DV demuxer can be easily implemented together in a single IC.
摘要翻译：数字视频（DV）存储系统包括接收模块，接收输入信号并将输入信号转换成输入位流; 直接连接到所述接口模块的DV解复用器，用于接收所述输入比特流，其中所述DV解复用器将所述输入比特流中的接收块解复用为至少在音频部分中的视频部分和音频块中的视频块; 以及耦合到DV解复用器的存储器以用于存储视频块和音频块的存储器。通过将接口模块直接连接到DV解复用器，并且通过不缓冲接口模块和DV解复用器之外的输入位流，大大减少了存储器的存储器带宽需求，并且接口模块和DV解复用器可以可以在单个IC中轻松实现。

9. 发明申请

US20050156233A1 Stacked gate flash memory device and method of fabricating the same 有权
标题翻译：堆叠式闪存器件及其制造方法
公开(公告)号：US20050156233A1
公开(公告)日：2005-07-21
申请号：US11076499
申请日：2005-03-09
申请人： Chi-Hui Lin
发明人： Chi-Hui Lin
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/423 , H01L29/788 , H01L29/76 , H01L21/336
CPC分类号： H01L27/11556 , H01L27/115 , H01L29/42336 , H01L29/7883
摘要： A stacked gate flash memory device and method of fabricating the same. A cell of the stacked gate flash memory device is disposed in a cell trench within a substrate to achieve higher integration of memory cells.
摘要翻译：堆叠式栅极闪存器件及其制造方法。层叠栅极闪存器件的单元被布置在衬底内的单元沟槽中，以实现存储单元的更高集成度。

10. 发明授权

US06916715B2 Method for fabricating a vertical NROM cell 有权
标题翻译：制造垂直NROM电池的方法
公开(公告)号：US06916715B2
公开(公告)日：2005-07-12
申请号：US10694155
申请日：2003-10-27
申请人： Ching-Nan Hsiao , Chi-Hui Lin , Chung-Lin Huang , Ying-Cheng Chuang
发明人： Ching-Nan Hsiao , Chi-Hui Lin , Chung-Lin Huang , Ying-Cheng Chuang
IPC分类号： H01L21/336 , H01L21/8234 , H01L21/8246 , H01L27/115 , H01L27/148
CPC分类号： H01L27/11568 , H01L27/115
摘要： A method for fabricating a vertical nitride read-only memory (NROM) cell. A substrate having at least one trench is provided. A spacer is formed over the sidewall of the trench. Subsequently, ion implantation is performed on the substrate using the spacer as a mask to form doping areas as bit lines in the substrate near its surface and the bottom of the trench. Bit line oxides are formed over each of the doping areas. After the spacer is removed, a conformable insulating layer as gate dielectric is deposited on the sidewall of the trench and the surface of the bit line oxide. Finally, a conductive layer as a word line is deposited over the insulating layer and fills in the trench.
摘要翻译：一种用于制造垂直氮化物只读存储器（NROM）单元的方法。提供具有至少一个沟槽的衬底。间隔件形成在沟槽的侧壁上。随后，使用间隔物作为掩模在衬底上进行离子注入，以在沟槽的表面和底部附近的衬底中形成作为位线的掺杂区域。在每个掺杂区域上形成位线氧化物。在移除间隔物之后，在沟槽的侧壁和位线氧化物的表面上沉积作为栅极电介质的适形绝缘层。最后，作为字线的导电层沉积在绝缘层上并填充在沟槽中。

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