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1. 发明授权

US5832241A Data consistency across a bus transactions that impose ordering constraints 失效
标题翻译：跨总线事务的数据一致性，强加排序约束
公开(公告)号：US5832241A
公开(公告)日：1998-11-03
申请号：US878660
申请日：1997-06-19
申请人： Charles B. Guy , Bruce Young , Norman Rasmussen
发明人： Charles B. Guy , Bruce Young , Norman Rasmussen
IPC分类号： G06F13/40 , H01J13/00
CPC分类号： G06F13/4004
摘要： A bus bridge is disclosed that handles bus transactions that must be completed on a destination bus before being completed on an originating bus by indicating a retry to delay such bus transactions on the originating bus while completing such bus transactions on the destination bus.
摘要翻译：公开了一种总线桥，其处理在通过始发总线完成之前必须在目的地总线上完成的总线事务，通过在目的地总线上完成这样的总线事务处指示重试来延迟始发总线上的总线事务。

2. 发明授权

US5191649A Multiprocessor computer system with data bus and ordered and out-of-order split data transactions 失效
标题翻译：具有数据总线和有序和无序拆分数据事务的多处理器计算机系统
公开(公告)号：US5191649A
公开(公告)日：1993-03-02
申请号：US631892
申请日：1990-12-21
申请人： Sudarshan B. Cadambi , Charles B. Guy , David R. Gray , Mark A. Gonzales
发明人： Sudarshan B. Cadambi , Charles B. Guy , David R. Gray , Mark A. Gonzales
IPC分类号： G06F15/17
CPC分类号： G06F15/17
摘要： A method of transferring data in response to a read command in a computer system having a plurality of processors coupled to an address bus, a command bus and a data bus is described. A first processor generates and sends the read command to read a first data from a second processor. The second processor then determines with which one of (1) the first data and (2) a read response command and the first data it desires to respond to the read command. If the second processor determines to respond with the first data, then it acknowledges receipt of the read command and performs an ordered response in which the command and address buses are released and only the first data is later sent to the first processor via the data bus when available. If the second processor determines to respond with the read response command and the first data, then it acknowledges receipt of the read command and performs an out-of-order response in which the access of the command and address buses is first released and gained again by arbitration when the first data is determined to be available in the second processor. The second processor then gains the access of the data bus when the data bus is free of any data transaction. The read response command and its address and the first data are then issued to the first processor.
摘要翻译：描述了在具有耦合到地址总线，命令总线和数据总线的多个处理器的计算机系统中响应于读取命令传送数据的方法。第一处理器产生并发送读取命令以从第二处理器读取第一数据。然后，第二处理器确定（1）第一数据中的哪一个和（2）读响应命令及其希望对读命令作出响应的第一数据。如果第二处理器确定用第一数据进行响应，则其确认读取命令的接收并且执行其中命令和地址总线被释放的有序响应，并且仅第一数据稍后经由数据总线发送到第一处理器有空的时候。如果第二处理器确定使用读取响应命令和第一个数据进行响应，则它确认接收到读取命令并且执行无效响应，其中命令和地址总线的访问首先被释放并再次获得当第一数据被确定为在第二处理器中可用时通过仲裁。然后当数据总线没有任何数据事务时，第二处理器获得数据总线的访问。然后，将读取响应命令及其地址和第一数据发布到第一处理器。

3. 发明授权

US5282272A Interrupt distribution scheme for a computer bus 失效
标题翻译：计算机总线的中断分配方案
公开(公告)号：US5282272A
公开(公告)日：1994-01-25
申请号：US10486
申请日：1993-01-28
申请人： Charles B. Guy , Sudarshan B. Cadambi , Michael J. Gutmann , Narjala Bhasker , Jim R. Trethewey , Brian J. McArdle
发明人： Charles B. Guy , Sudarshan B. Cadambi , Michael J. Gutmann , Narjala Bhasker , Jim R. Trethewey , Brian J. McArdle
IPC分类号： G06F9/48 , G06F9/46
CPC分类号： G06F9/4812
摘要： A method of handling processor to processor interrupt requests in a multiprocessing computer bus environment is described. This method allows a multiple-tiered, increasing priority, interrupt request scheme. This method also allows processor to processor directed interrupt requests, processor to one processor of a group of processors interrupt requests, and processor to all processors of a group of processors interrupt requests.
摘要翻译：描述了在多处理计算机总线环境中处理处理器处理器中断请求的方法。这种方法允许多层次，优先级高的中断请求方案。这种方法还允许处理器对处理器定向的中断请求，处理器到一组处理器的一组处理器中断请求，以及处理器到一组处理器的所有处理器中断请求。

4. 发明授权

US5261109A Distributed arbitration method and apparatus for a computer bus using arbitration groups 失效
标题翻译：使用仲裁组的计算机总线的分布式仲裁方法和装置
公开(公告)号：US5261109A
公开(公告)日：1993-11-09
申请号：US6138
申请日：1993-01-19
申请人： Sudarshan B. Cadambi , Charles B. Guy , David R. Gray , Mark A. Gonzales
发明人： Sudarshan B. Cadambi , Charles B. Guy , David R. Gray , Mark A. Gonzales
IPC分类号： G06F13/368 , G06F13/374 , G06F13/36
CPC分类号： G06F13/374 , G06F13/368
摘要： A distributed method for arbitrating access to a common bus in a multiple processor environment is described. This method provides for fairness where multiple processors are vying for access to a global memory. An apparatus for arbitrating access to a common bus in a multiple processor environment is also described. This apparatus provides for priority determination of each processor upon system reset and provides for fairness where multiple processors are vying for access to a global memory.
摘要翻译：描述了用于在多处理器环境中仲裁访问公共总线的分布式方法。该方法提供了多个处理器争取访问全局内存的公平性。还描述了用于在多处理器环境中仲裁访问公共总线的装置。该装置在系统复位时提供每个处理器的优先级确定，并且在多个处理器竞争访问全局存储器时提供公平性。

5. 发明授权

US5778424A Distributed placement, variable-size cache architecture 失效
标题翻译：分布式放置，可变大小缓存架构
公开(公告)号：US5778424A
公开(公告)日：1998-07-07
申请号：US56366
申请日：1993-04-30
申请人： Charles B. Guy
发明人： Charles B. Guy
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0862 , G06F12/0864 , G06F2212/601
摘要： A distributed variable-size cache placement architecture includes plural cache storage units (CSUs), each of which includes a CSU control logic, an address director, a data director, a placement array, placement logic (i.e., distribution controller), and a set associative memory for caching data. All CSUs in the architecture are connected over a communication network to a single processor interface and mainstore and which provides information to all CSUs about the status of each of the other CSUs. Any number of CSUs may be connected in parallel to provide a variable size cache. All CSUs sharing a processor interface utilize the same placement block size, contain the same number of sets of cache elements and use the same CSU placement mechanism.
摘要翻译：分布式可变大小缓存放置架构包括多个高速缓存存储单元（CSU），每个缓存存储单元包括CSU控制逻辑，地址引导器，数据引导器，放置阵列，放置逻辑（即，分配控制器）和一组用于缓存数据的关联内存。架构中的所有CSU都通过通信网络连接到单个处理器接口和主机，并向所有CSU提供关于每个其他CSU的状态的信息。任何数量的CSU可以并行连接以提供可变大小的缓存。共享处理器接口的所有CSU都使用相同的放置块大小，包含相同数量的缓存元素组并使用相同的CSU放置机制。

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