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1. 发明授权

US09879664B2 Device and method for controlling compressor of vehicles to accumulate cold air energy in an evaporator during a speed-reducing condition and using the latter in a release condition 有权
公开(公告)号：US09879664B2
公开(公告)日：2018-01-30
申请号：US12951505
申请日：2010-11-22
申请人： Jae Woong Kim , Chang Won Lee , Kilyong Jang
发明人： Jae Woong Kim , Chang Won Lee , Kilyong Jang
IPC分类号： F25B1/00 , F25B49/00 , B60H1/32 , F25D17/04 , F04B35/00 , F04B49/06 , B60H1/00
CPC分类号： F04B35/002 , B60H1/00764 , B60H1/00778 , B60H1/00835 , B60H1/00849 , B60H1/00878 , B60H1/3208 , B60H2001/3266 , B60H2001/327 , F04B49/065 , F04B2203/0604 , F04B2203/0605 , F04B2203/0607 , F04B2205/10 , F04B2207/03
摘要： A device for controlling a compressor of vehicles may include a sensor module including a cabin temperature sensor, an outdoor temperature sensor, an evaporator temperature sensor detecting a temperature of cooling medium in an evaporator, a vehicle speed sensor, and a brake sensor, an injector, an air conditioning system including a condenser, an evaporator, the compressor, a temperature control door controlling a temperature of air flowing into a cabin, an intake door selectively distributing an inner air or an outer air into the cabin, and a blower blowing the air to the intake door, and a controller controlling the injector and the air conditioning system, wherein the controller accumulates a cold air energy by increasing an operation of the compressor if a speed-reducing condition occurs, and the air conditioning system uses the accumulated cold air energy by decreasing the operation of the compressor if a release condition occurs.

2. 发明授权

US08916104B2 Exhaust gas denitrifying system having noise-reduction structure 有权
标题翻译：具有降噪结构的废气脱氮系统
公开(公告)号：US08916104B2
公开(公告)日：2014-12-23
申请号：US13220303
申请日：2011-08-29
申请人： Soo-Tae Lee , Ok-Ryeol Song , Chang-Won Lee , Ha-Geun Kang
发明人： Soo-Tae Lee , Ok-Ryeol Song , Chang-Won Lee , Ha-Geun Kang
IPC分类号： B01D53/56 , B01D53/94 , F01N3/28 , B01D53/86 , F01N3/20 , F01N1/10 , F01N13/00 , F01N3/30
CPC分类号： B01D53/8631 , B01D53/8696 , B01D2251/2067 , F01N1/10 , F01N3/2066 , F01N3/2828 , F01N3/2885 , F01N3/2892 , F01N3/30 , F01N13/0097 , F01N2230/04 , F01N2240/20 , F01N2330/06 , F01N2330/32 , F01N2330/325 , F01N2570/14 , F01N2610/02 , Y02A50/2344 , Y02T10/24
摘要： An exhaust gas denitrifying system having a noise-reduction structure includes a reactor in which a chemical reaction that converts nitrogen oxides included in exhaust gas into nitrogen by denitrifying the nitrogen oxides using a catalyst takes place. The reactor includes a catalytic filter unit coated with a catalyst and provided with a plurality of through-holes through which exhaust gas passes; and a noise-reducing unit for removing noise from the exhaust gas denitrified by the catalytic filter unit. The reactor denitrifies the nitrogen oxides, and simultaneously reduces the noise, thus reducing the size of the exhaust gas denitrifying system.
摘要翻译：具有降噪结构的废气脱氮系统包括反应器，其中发生通过使用催化剂使氮氧化物脱氮而将排气中包含的氮氧化物转化为氮的化学反应。反应器包括涂覆有催化剂的催化过滤器单元并且设置有多个通过排气的通孔; 以及噪声降低单元，用于消除由催化过滤器单元反硝化的废气中的噪声。反应器使氮氧化物脱氮，同时降低噪声，从而减小废气脱氮系统的尺寸。

3. 发明申请

US20120075692A1 MULTI-LAYERED HYBRID METAMATERIAL STRUCTURE 有权
标题翻译：多层混合金属结构
公开(公告)号：US20120075692A1
公开(公告)日：2012-03-29
申请号：US13095100
申请日：2011-04-27
申请人： Chan-wook BAIK , Jong-min KIM , Chang-won LEE
发明人： Chan-wook BAIK , Jong-min KIM , Chang-won LEE
IPC分类号： H01S5/10 , H01S3/08
CPC分类号： G02F1/21 , G02F1/218 , G02F2202/30 , G02F2203/13 , H01P1/2005 , H01P7/082 , H01Q15/0026 , H01Q15/0086
摘要： A metamaterial structure is provided, including a substrate and a plurality of resonators that are provided on different surfaces of the substrate or different layers of the substrate. The resonators have resonance characteristics different from each other, and the metamaterial structure has a permittivity, a permeability, and a refractive index respectively different from those of the substrate in a predetermined frequency bandwidth.
摘要翻译：提供超材料结构，其包括衬底和设置在衬底的不同表面或衬底的不同层上的多个谐振器。谐振器具有彼此不同的共振特性，并且超材料结构在预定频率带宽中具有分别不同于衬底的介电常数，磁导率和折射率。

4. 发明申请

US20120057215A1 SURFACE PLASMON POLARITON MODULATOR 有权
标题翻译：表面等离子体POLARITON调制器
公开(公告)号：US20120057215A1
公开(公告)日：2012-03-08
申请号：US13090453
申请日：2011-04-20
申请人： Hwansoo SUH , Chang Won LEE , Yeonsang PARK , Jineun KIM
发明人： Hwansoo SUH , Chang Won LEE , Yeonsang PARK , Jineun KIM
IPC分类号： G02F1/09 , G02F1/11 , G02F1/01
CPC分类号： G02F1/00 , G02B6/1226 , G02F1/01 , G02F1/035 , G02F1/29 , G02F2203/10
摘要： A surface plasmon polariton modulator capable of locally varying a physical property of a dielectric material to control a surface plasmon polariton. The surface plasmon polariton modulator includes a dielectric layer, including first and second dielectric portions, which is interposed between two metal layers. The second dielectric portion has a refractive index which varies with an electric field, a magnetic field, heat, a sound wave, or a chemical and/or biological operation applied thereto. The surface plasmon polariton modulator is configured to control one of an advancing direction, an intensity, a phase, or the like of a surface plasmon using an electric signal. The surface plasmon polariton modulator can operate as a surface plasmon polariton multiplexer or a surface plasmon polariton demultiplexer.
摘要翻译：能够局部地改变介电材料的物理性质以控制表面等离子体激元的表面等离子体激元调制器。表面等离子体激元调制器包括介于介电层，介电层包括介于两个金属层之间的第一和第二电介质部分。第二电介质部分具有随着施加到其上的电场，磁场，热，声波或化学和/或生物操作而变化的折射率。表面等离子体激元调制器被配置为使用电信号来控制表面等离子体的前进方向，强度，相位等之一。表面等离子体激元调制器可以作为表面等离子体激元多极化多路复用器或表面等离子体激元解离器来操作。

5. 发明授权

US07998810B2 Methods of forming integrated circuit devices having stacked gate electrodes 有权
标题翻译：形成具有层叠栅电极的集成电路器件的方法
公开(公告)号：US07998810B2
公开(公告)日：2011-08-16
申请号：US12424922
申请日：2009-04-16
申请人： Byung-hee Kim , Gil-heyun Choi , Sang-woo Lee , Chang-won Lee , Jin-ho Park , Eun-ji Jung , Jeong-gil Lee
发明人： Byung-hee Kim , Gil-heyun Choi , Sang-woo Lee , Chang-won Lee , Jin-ho Park , Eun-ji Jung , Jeong-gil Lee
IPC分类号： H01L21/336
CPC分类号： H01L27/11521 , H01L21/28273 , H01L29/66545
摘要： A method of forming a gate electrode of a semiconductor device is provided, the method including: forming a plurality of stacked structures each comprising a tunnel dielectric layer, a first silicon layer for floating gates, an intergate dielectric layer, a second silicon layer for control gates, and a mask pattern, on a semiconductor substrate in the stated order; forming a first interlayer dielectric layer between the plurality of stacked structures so that a top surface of the mask pattern is exposed; selectively removing the mask pattern of which the top surface is exposed; forming a third silicon layer in an area from which the hard disk layer was removed, and forming a silicon layer comprising the third silicon layer and the second silicon layer; recessing the first interlayer dielectric layer so that an upper portion of the silicon layer protrudes over the he first interlayer dielectric layer; and forming a metal silicide layer on the upper portion of the silicon layer.
摘要翻译：提供一种形成半导体器件的栅电极的方法，所述方法包括：形成多个堆叠结构，每个堆叠结构包括隧道介电层，用于浮置栅极的第一硅层，栅极间介电层，用于控制的第二硅层栅极和掩模图案，以所述顺序在半导体衬底上; 在所述多个堆叠结构之间形成第一层间电介质层，使得所述掩模图案的顶表面露出; 选择性地去除其顶表面暴露的掩模图案; 在去除所述硬盘层的区域中形成第三硅层，以及形成包含所述第三硅层和所述第二硅层的硅层; 使第一层间电介质层凹陷，使得硅层的上部突出在第一层间介电层上; 以及在所述硅层的上部形成金属硅化物层。

6. 发明授权

US07994815B2 Cross-point latch and method of operating the same 有权
标题翻译：交叉点闩锁及其操作方法
公开(公告)号：US07994815B2
公开(公告)日：2011-08-09
申请号：US11902416
申请日：2007-09-21
申请人： Hyun-jong Chung , Sun-ae Seo , Chang-won Lee , Dae-young Jeon , Ran-ju Jung , Dong-chul Kim , Ji-young Bae
发明人： Hyun-jong Chung , Sun-ae Seo , Chang-won Lee , Dae-young Jeon , Ran-ju Jung , Dong-chul Kim , Ji-young Bae
IPC分类号： H03K19/173
CPC分类号： H03K3/40 , G11C13/00 , G11C13/0007 , G11C2213/32 , G11C2213/77
摘要： Provided is a cross-point latch and a method of operating the cross-point latch. The cross-point latch includes a signal line, two control lines crossing the signal line, and unipolar switches disposed at crossing points between the signal line and the control lines.
摘要翻译：提供了交叉点锁存器和操作交叉点锁存器的方法。交叉点锁存器包括信号线，与信号线交叉的两个控制线，以及设置在信号线与控制线之间的交叉点处的单极开关。

7. 发明授权

US07968410B2 Method of fabricating a semiconductor device using a full silicidation process 有权
标题翻译：使用全硅化工艺制造半导体器件的方法
公开(公告)号：US07968410B2
公开(公告)日：2011-06-28
申请号：US12460945
申请日：2009-07-27
申请人： Eun-ji Jung , Sang-woo Lee , Jeong-gil Lee , Gil-heyun Choi , Chang-won Lee , Byung-hee Kim , Jin-ho Park
发明人： Eun-ji Jung , Sang-woo Lee , Jeong-gil Lee , Gil-heyun Choi , Chang-won Lee , Byung-hee Kim , Jin-ho Park
IPC分类号： H01L21/336
CPC分类号： H01L27/11573 , H01L21/28123 , H01L21/28282
摘要： A method of fabricating a semiconductor device includes: forming a first polysilicon layer having a first thickness in a peripheral circuit region formed on a substrate; forming a stack structure comprising a first tunneling insulating layer, a charge trap layer, and a blocking insulating layer in a memory cell region formed on the substrate; forming a second polysilicon layer having a second thickness that is less than the first thickness on the blocking insulating layer; and forming gate electrodes by siliciding the first and second polysilicon layers.
摘要翻译：一种制造半导体器件的方法包括：在形成在衬底上的外围电路区域中形成具有第一厚度的第一多晶硅层; 在形成在所述基板上的存储单元区域中形成包括第一隧道绝缘层，电荷陷阱层和阻挡绝缘层的堆叠结构; 在所述阻挡绝缘层上形成具有小于所述第一厚度的第二厚度的第二多晶硅层; 以及通过硅化第一和第二多晶硅层来形成栅电极。

8. 发明授权

US07772643B2 Methods of fabricating semiconductor device having a metal gate pattern 有权
标题翻译：制造具有金属栅极图案的半导体器件的方法
公开(公告)号：US07772643B2
公开(公告)日：2010-08-10
申请号：US12457323
申请日：2009-06-08
申请人： Ja-Hum Ku , Chang-Won Lee , Seong-Jun Heo , Sun-Pil Youn , Sung-Man Kim
发明人： Ja-Hum Ku , Chang-Won Lee , Seong-Jun Heo , Sun-Pil Youn , Sung-Man Kim
IPC分类号： H01L29/94 , H01L29/78
CPC分类号： H01L21/823437 , H01L21/28247 , H01L29/4941 , H01L29/6656
摘要： A method of fabricating a semiconductor device having a metal gate pattern is provided in which capping layers are used to control the relative oxidation rates of portions of the metal gate pattern during a oxidation process. The capping layer may be a multilayer structure and may be etched to form insulating spacers on the sidewalls of the metal gate pattern. The capping layer(s) allow the use of a selective oxidation process, which may be a wet oxidation process utilizing partial pressures of both H2O and H2 in an H2-rich atmosphere, to oxidize portions of the substrate and metal gate pattern while suppressing the oxidation of metal layers that may be included in the metal gate pattern. This allows etch damage to the silicon substrate and edges of the metal gate pattern to be reduced while substantially maintaining the original thickness of the gate insulating layer and the conductivity of the metal layer(s).
摘要翻译：提供一种制造具有金属栅极图案的半导体器件的方法，其中使用覆盖层来控制氧化过程中金属栅极图案的部分的相对氧化率。覆盖层可以是多层结构，并且可以被蚀刻以在金属栅极图案的侧壁上形成绝缘间隔物。封盖层允许使用选择性氧化工艺，其可以是在富H2气氛中使用H 2 O和H 2的分压的湿式氧化工艺，以氧化基板和金属栅极图案的部分，同时抑制可以包括在金属栅极图案中的金属层的氧化。这允许对硅衬底的蚀刻损伤和金属栅极图案的边缘减小，同时基本上保持栅极绝缘层的原始厚度和金属层的导电性。

9. 发明授权

US07696552B2 Semiconductor devices including high-k dielectric materials 失效
标题翻译：包括高k电介质材料的半导体器件
公开(公告)号：US07696552B2
公开(公告)日：2010-04-13
申请号：US11227541
申请日：2005-09-15
申请人： Sun-Pil Youn , Chang-Won Lee , Woong-Hee Sohn , Gil-Heyun Choi , Jong-Ryeol Yoo , Dong-Chan Lim , Jae-Hwa Park , Byung-Hak Lee , Hee-Sook Park
发明人： Sun-Pil Youn , Chang-Won Lee , Woong-Hee Sohn , Gil-Heyun Choi , Jong-Ryeol Yoo , Dong-Chan Lim , Jae-Hwa Park , Byung-Hak Lee , Hee-Sook Park
IPC分类号： H01L27/108 , H01L29/94
CPC分类号： H01L27/11526 , H01L21/82345 , H01L27/105 , H01L27/1052 , H01L27/11546
摘要： A semiconductor device includes a first conductive layer on a semiconductor substrate, a dielectric layer including a high-k dielectric material on the first conductive layer, a second conductive layer including polysilicon doped with P-type impurities on the dielectric layer, and a third conductive layer including a metal on the second conductive layer. In some devices, a first gate structure is formed in a main cell region and includes a tunnel oxide layer, a floating gate, a first high-k dielectric layer, and a control gate. The control gate includes a layer of polysilicon doped with P-type impurities and a metal layer. A second gate structure is formed outside the main cell region and includes a tunnel oxide layer, a conductive layer, and a metal layer. A third gate structure is formed in a peripheral cell region and includes a tunnel oxide, a conductive layer, and a high-k dielectric layer having a width narrower than the conductive layer. Method embodiments are also disclosed.
摘要翻译：半导体器件包括在半导体衬底上的第一导电层，在第一导电层上包括高k电介质材料的电介质层，在电介质层上掺杂有P型杂质的多晶硅的第二导电层，以及第三导电层层，其包括在第二导电层上的金属。在一些器件中，第一栅极结构形成在主单元区域中，并且包括隧道氧化物层，浮置栅极，第一高k电介质层和控制栅极。控制栅极包括掺杂有P型杂质和金属层的多晶硅层。第二栅极结构形成在主单元区域的外部，并且包括隧道氧化物层，导电层和金属层。第三栅极结构形成在周边单元区域中，并且包括具有比导电层窄的宽度的隧道氧化物，导电层和高k电介质层。还公开了方法实施例。

10. 发明授权

US07521316B2 Methods of forming gate structures for semiconductor devices 有权
标题翻译：形成半导体器件栅极结构的方法
公开(公告)号：US07521316B2
公开(公告)日：2009-04-21
申请号：US11221062
申请日：2005-09-07
申请人： Woong-Hee Sohn , Chang-Won Lee , Sun-Pil Youn , Gil-Heyun Choi , Byung-Hak Lee , Jong-Ryeol Yoo , Hee-Sook Park
发明人： Woong-Hee Sohn , Chang-Won Lee , Sun-Pil Youn , Gil-Heyun Choi , Byung-Hak Lee , Jong-Ryeol Yoo , Hee-Sook Park
IPC分类号： H01L21/00
CPC分类号： H01L21/28273 , H01L29/42324
摘要： Methods of forming a semiconductor device may include forming a tunnel oxide layer on a semiconductor substrate, forming a gate structure on the tunnel oxide layer, forming a leakage barrier oxide, and forming an insulating spacer. More particularly, the tunnel oxide layer may be between the gate structure and the substrate, and the gate structure may include a first gate electrode on the tunnel oxide layer, an inter-gate dielectric on the first gate electrode, and a second gate electrode on the inter-gate dielectric with the inter-gate dielectric between the first and second gate electrodes. The leakage barrier oxide may be formed on sidewalls of the second gate electrode. The insulating spacer may be formed on the leakage barrier oxide with the leakage barrier oxide between the insulating spacer and the sidewalls of the second gate electrode. In addition, the insulating spacer and the leakage barrier oxide may include different materials. Related structures are also discussed.
摘要翻译：形成半导体器件的方法可以包括在半导体衬底上形成隧道氧化物层，在隧道氧化物层上形成栅极结构，形成漏电阻氧化物，形成绝缘衬垫。更具体地，隧道氧化物层可以在栅极结构和衬底之间，并且栅极结构可以包括隧道氧化物层上的第一栅极电极，第一栅电极上的栅极间电介质和第二栅电极所述栅极间电介质与所述第一和第二栅电极之间的栅极间电介质。漏电阻氧化物可以形成在第二栅电极的侧壁上。绝缘间隔物可以在绝缘隔离物和第二栅电极的侧壁之间的泄漏阻挡氧化物形成在漏电阻氧化物上。此外，绝缘间隔物和漏电阻氧化物可以包括不同的材料。还讨论了相关结构。

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