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    • 6. 发明授权
    • Dynamic random access memory cell and method for fabricating the same
    • 动态随机存取存储单元及其制造方法
    • US5500544A
    • 1996-03-19
    • US228021
    • 1994-04-15
    • Chan K. ParkYo H. KohSeong M. HwangKwang M. Roh
    • Chan K. ParkYo H. KohSeong M. HwangKwang M. Roh
    • H01L23/522H01L21/768H01L21/8242H01L27/10H01L27/108H01L21/265
    • H01L27/10852H01L27/10808H01L2924/0002Y10S257/908Y10S257/909
    • The DRAM cell comprises a bit line having a topology higher than a plate electrode atop a dielectric film formed on a charge storage electrode, wherein the bit line is connected with a drain region and also with an oxide film which is formed at a predetermined portion of the plate electrode placed above the drain region, the oxide film playing a role in insulating said plate electrode from said bit line.Serving as an insulator between the plate electrode and the bit line, the oxide film is formed by oxidizing the plate electrode adjacent to the bit line. By virtue of this oxide film, there can be secured allowance for the formation of highly integrated device.A DRAM cell can be fabricated in fewer process steps according to the present invention. The DRAM cell is superior in reliability even if it is highly integrated since the area of the capacitor is largely secured without any short phenomenon of bit line.
    • DRAM单元包括在电荷存储电极上形成的电介质膜的上方具有比平板电极高的拓扑结构的位线,其中位线与漏极区域连接,并且还与形成在预定部分的氧化物膜 所述平板电极位于所述漏极区域的上方,所述氧化物膜起绝缘所述平板电极与所述位线的作用。 作为平板电极和位线之间的绝缘体,氧化膜通过邻近位线氧化板电极而形成。 通过这种氧化膜,可以确保形成高集成度的装置。 根据本发明,可以以较少的工艺步骤制造DRAM单元。 即使高度集成,DRAM单元也具有优异的可靠性,因为电容器的面积被大大地保证,而没有任何短的位线现象。