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1. 发明申请

US20130299815A1 ELECTRONIC DEVICES 有权
标题翻译：电子设备
公开(公告)号：US20130299815A1
公开(公告)日：2013-11-14
申请号：US13988399
申请日：2011-11-25
申请人： Martin Jackson , Catherine Ramsdale , Jerome Joimel
发明人： Martin Jackson , Catherine Ramsdale , Jerome Joimel
IPC分类号： H01L51/05
CPC分类号： H01L51/0512 , H01L27/283 , H01L51/0541 , H01L51/0545
摘要： A device comprising an array of transistors, including: patterned conductive layers located at lower and upper levels in a stack of layers on a substrate, which patterned conductive layers define gate conductors and source-drain electrodes of the array of transistors; wherein the stack of layers further comprises a dielectric layer below said lower level, and a further patterned conductive layer below said dielectric layer; and wherein said further patterned conductive layer both provides an electrical function in said array of transistors via said dielectric layer, and defines openings via which the dielectric layer serves to increase the strength of adhesion between the device substrate and the patterned conductive layer at said lower level.
摘要翻译：一种包括晶体管阵列的器件，包括：位于衬底上的层叠层中的下层和上层的图案化导电层，所述图案化导电层限定晶体管阵列的栅极导体和源 - 漏电极; 其中所述层叠层还包括位于所述下层下面的电介质层，以及在所述介电层下方的另外的图案化导电层; 并且其中所述另外的图案化导电层都经由所述介电层在所述晶体管阵列中提供电功能，并且限定开口，所述介电层用于通过所述开口增加所述下层的器件基板和图案化导电层之间的粘合强度。

2. 发明授权

US09331132B2 Multiple conductive layer TFT 有权
标题翻译：多导电层TFT
公开(公告)号：US09331132B2
公开(公告)日：2016-05-03
申请号：US11910733
申请日：2006-04-05
申请人： Kieran Reynolds , Catherine Ramsdale , Kevin Jacobs , William Reeves
发明人： Kieran Reynolds , Catherine Ramsdale , Kevin Jacobs , William Reeves
IPC分类号： H01L29/08 , H01L27/32
CPC分类号： H01L27/283 , H01L23/5286 , H01L27/3262 , H01L27/3265 , H01L27/3274 , H01L27/3276 , H01L51/0022 , H01L51/0512 , H01L51/105 , H01L2227/323
摘要： A multiple layer pixel architecture for an active matrix display is provided in which a common bus line is formed on a metal level which is separate from that on which the gate electrodes of the thin-film transistors (TFTS) are formed. A multilayer electronic structure adapted to solution deposition, the structure includes a TFT for driving a pixel of an active matrix optoelectronic device and a capacitor for storing charge to maintain an electrical state of said active matrix pixel, wherein the structure includes a substrate bearing at least four conducting layers separeted by at least three dielectric layers, first and second ones of said conducting layers defining drain/source electrodes and a gate electrode of said transistor respectively, and third and fourth ones of said conducting layers defining respective first and second plates of said capacitor, and wherein said capacitor and said transistor are laterally positioned such that they overlap in a vertical direction.
摘要翻译：提供了一种用于有源矩阵显示器的多层像素架构，其中在与形成薄膜晶体管（TFTS）的栅电极的金属层上分开的金属层上形成公共总线。一种适于溶液沉积的多层电子结构，该结构包括用于驱动有源矩阵光电子器件的像素的TFT和用于存储电荷以维持所述有源矩阵像素的电状态的电容器，其中所述结构至少包括至少四个导电层由至少三个电介质层分隔开，所述导电层中的第一和第二导电层分别限定漏极/源电极和所述晶体管的栅电极，第三和第四导电层限定相应的第一和第二板电容器，并且其中所述电容器和所述晶体管被横向定位成使得它们在垂直方向上重叠。

3. 发明申请

US20060160277A1 Active layer island 有权
标题翻译：有源层岛
公开(公告)号：US20060160277A1
公开(公告)日：2006-07-20
申请号：US10542546
申请日：2004-01-19
申请人： Henning Sirringhaus , Catherine Ramsdale
发明人： Henning Sirringhaus , Catherine Ramsdale
IPC分类号： H01L51/40 , H01L21/84
CPC分类号： H01L21/00 , H01L51/0005 , H01L51/0022 , H01L51/0512 , H01L51/0541
摘要： A method for forming an electronic device including at least one electrically conductive and one semiconductive material deposited from solution, the method comprising: forming on the substrate a confinement structure consisting of a least a first zone and a second zone, depositing the electrically conductive material on the substrate, wherein the electrically conductive material is absent from both the first and second zone, and subsequently depositing the electrically semiconductive material from solution, wherein the semiconductive material is absent from the first zone, but not from the second zone.
摘要翻译：一种用于形成包括从溶液沉积的至少一种导电和一种半导体材料的电子器件的方法，所述方法包括：在所述衬底上形成由至少第一区和第二区组成的约束结构，将所述导电材料沉积在所述衬底，其中所述导电材料不在所述第一和第二区域中，并且随后从溶液沉积所述电半导体材料，其中所述半导体材料不存在于所述第一区域中，而不是来自所述第二区域。

4. 发明申请

US20140048806A1 ELECTRONIC DEVICE AND ITS METHOD OF MANUFACTURE 有权
标题翻译：电子器件及其制造方法
公开(公告)号：US20140048806A1
公开(公告)日：2014-02-20
申请号：US14008009
申请日：2012-03-30
申请人： Richard Price , Catherine Ramsdale
发明人： Richard Price , Catherine Ramsdale
IPC分类号： H01L21/268 , H01L29/786 , H01L29/66
CPC分类号： H01L21/268 , H01L21/428 , H01L29/6675 , H01L29/66757 , H01L29/66772 , H01L29/66969 , H01L29/78618 , H01L29/7869 , H01L29/78696 , H01L51/0027 , H01L51/105
摘要： A method of manufacturing an electronic device comprises: providing a layer of semiconductor material comprising a first portion, a second portion, and a third portion, the third portion connecting the first portion to the second portion and providing a semiconductive channel for electrical current flow between the first and second portions; providing a gate terminal arranged with respect to said third portion such that a voltage may be applied to the gate terminal to control an electrical conductivity of said channel; and processing at least one of the first and second portions so as to have an electrical conductivity greater than an electrical conductivity of the channel when no voltage is applied to the gate terminal. In certain embodiments, the processing comprises exposing at least one of the first and second portions to electromagnetic radiation. The first and second portions may be laser annealed to increase their conductivities.
摘要翻译：一种制造电子设备的方法包括：提供包括第一部分，第二部分和第三部分的半导体材料层，第三部分将第一部分连接到第二部分，并提供半导体通道，用于在第一和第二部分; 提供相对于所述第三部分布置的栅极端子，使得可以向栅极端子施加电压以控制所述沟道的导电性; 以及当没有电压施加到所述栅极端子时，处理所述第一部分和所述第二部分中的至少一个，使得具有大于所述沟道的电导率的导电性。在某些实施例中，处理包括将第一和第二部分中的至少一个暴露于电磁辐射。第一和第二部分可以被激光退火以增加它们的电导率。

5. 发明授权

US08652964B2 Method and apparatus for the formation of an electronic device 有权
标题翻译：用于形成电子装置的方法和装置
公开(公告)号：US08652964B2
公开(公告)日：2014-02-18
申请号：US13124207
申请日：2009-09-28
申请人： Dean Bradley Baker , Catherine Ramsdale , Martin Lewis , Rashmi Sachin Bhintade
发明人： Dean Bradley Baker , Catherine Ramsdale , Martin Lewis , Rashmi Sachin Bhintade
IPC分类号： H01L21/28 , H01L21/335
CPC分类号： H01L51/0018 , G03F7/165 , G03F7/42 , G03F7/425 , H01L51/105
摘要： A process of forming an electronic device, by forming the source and drain contacts using photolithography, incorporating a self-assembled monolayer (SAM) over the electrical contacts to form an increased work function of the source and drain electrodes and further forming more favorable charge injection properties or within the channel region to improve film morphology and therefore improve charge transport. The SAM material is added to the photoresist stripper during a step of the photolithography process of forming electrical contacts.
摘要翻译：一种形成电子器件的工艺，通过使用光刻法形成源极和漏极触点，在电触头上并入自组装单层（SAM）以形成增加的源电极和漏电极的功函数并进一步形成更有利的电荷注入性质或通道区域内，以改善膜形态，从而改善电荷传输。在形成电接触的光刻工艺的步骤期间，将SAM材料加入到光致抗蚀剂剥离器中。

6. 发明申请

US20110237053A1 Method and Apparatus for the Formation of an Electronic Device 有权
标题翻译：用于形成电子装置的方法和装置
公开(公告)号：US20110237053A1
公开(公告)日：2011-09-29
申请号：US13124207
申请日：2009-09-28
申请人： Dean Baker , Catherine Ramsdale , Martin Lewis
发明人： Dean Baker , Catherine Ramsdale , Martin Lewis
IPC分类号： H01L21/20 , G03F7/42
CPC分类号： H01L51/0018 , G03F7/165 , G03F7/42 , G03F7/425 , H01L51/105
摘要： A process of forming an electronic device, by forming the source and drain contacts using photolithography, incorporating a self-assembled monolayer (SAM) over the electrical contacts to form an increased work function of the source and drain electrodes and further forming more favorable charge injection properties or within the channel region to improve film morphology and therefore improve charge transport. The SAM material is added to the photoresist stripper during a step of the photolithography process of forming electrical contacts.
摘要翻译：一种形成电子器件的工艺，通过使用光刻法形成源极和漏极触点，在电触头上并入自组装单层（SAM）以形成增加的源电极和漏电极的功函数并进一步形成更有利的电荷注入性质或通道区域内，以改善膜形态，从而改善电荷传输。在形成电接触的光刻工艺的步骤期间，将SAM材料加入到光致抗蚀剂剥离器中。

7. 发明授权

US07709306B2 Active layer island 有权
标题翻译：有源层岛
公开(公告)号：US07709306B2
公开(公告)日：2010-05-04
申请号：US10542546
申请日：2004-01-19
申请人： Henning Sirringhaus , Catherine Ramsdale
发明人： Henning Sirringhaus , Catherine Ramsdale
IPC分类号： H01L21/00 , H01L21/84
CPC分类号： H01L21/00 , H01L51/0005 , H01L51/0022 , H01L51/0512 , H01L51/0541
摘要： A method for forming an electronic device including at least one electrically conductive and one semiconductive material deposited from solution, the method comprising: forming on the substrate a confinement structure consisting of a least a first zone and a second zone, depositing the electrically conductive material on the substrate, wherein the electrically conductive material is absent from both the first and second zone, and subsequently depositing the electrically semiconductive material from solution, wherein the semiconductive material is absent from the first zone, but not from the second zone.
摘要翻译：一种用于形成包括从溶液沉积的至少一种导电和一种半导体材料的电子器件的方法，所述方法包括：在所述衬底上形成由至少第一区和第二区组成的约束结构，将所述导电材料沉积在所述衬底，其中所述导电材料不在所述第一和第二区域中，并且随后从溶液沉积所述电半导体材料，其中所述半导体材料不存在于所述第一区域中，而不是来自所述第二区域。

8. 发明申请

US20070232035A1 Electronic Device 有权
标题翻译：电子设备
公开(公告)号：US20070232035A1
公开(公告)日：2007-10-04
申请号：US11596211
申请日：2005-05-16
申请人： Catherine Ramsdale , Henning Sirringhaus , Timothy Von Werne
发明人： Catherine Ramsdale , Henning Sirringhaus , Timothy Von Werne
IPC分类号： H01L21/20
CPC分类号： H01L51/0541 , B82Y10/00 , B82Y30/00 , H01L51/0004 , H01L51/0036 , H01L51/0516 , H01L51/105
摘要： A technique for high-resolution surface energy assisted patterning of semiconductor active layer islands on top of an array of predefined source-drain electrodes without requiring an additional process step for surface energy patterning.
摘要翻译：用于高分辨率表面能量辅助图案化半导体有源层岛的技术，在预定义的源极 - 漏极电极阵列之上，而不需要用于表面能量图案化的附加工艺步骤。

9. 发明授权

US09530649B2 Semiconductor electronic devices and methods of manufacture thereof 有权
标题翻译：半导体电子器件及其制造方法
公开(公告)号：US09530649B2
公开(公告)日：2016-12-27
申请号：US14008009
申请日：2012-03-30
申请人： Richard Price , Catherine Ramsdale
发明人： Richard Price , Catherine Ramsdale
IPC分类号： H01L29/66 , H01L21/268 , H01L29/786
CPC分类号： H01L21/268 , H01L21/428 , H01L29/6675 , H01L29/66757 , H01L29/66772 , H01L29/66969 , H01L29/78618 , H01L29/7869 , H01L29/78696 , H01L51/0027 , H01L51/105
摘要： A method of manufacturing an electronic device comprises: providing a layer of semiconductor material comprising a first portion, a second portion, and a third portion, the third portion connecting the first portion to the second portion and providing a semiconductive channel for electrical current flow between the first and second portions; providing a gate terminal arranged with respect to said third portion such that a voltage may be applied to the gate terminal to control an electrical conductivity of said channel; and processing at least one of the first and second portions so as to have an electrical conductivity greater than an electrical conductivity of the channel when no voltage is applied to the gate terminal. In certain embodiments, the processing comprises exposing at least one of the first and second portions to electromagnetic radiation. The first and second portions may be laser annealed to increase their conductivities.
摘要翻译：一种制造电子设备的方法包括：提供包括第一部分，第二部分和第三部分的半导体材料层，第三部分将第一部分连接到第二部分，并提供半导体通道，用于在第一和第二部分; 提供相对于所述第三部分布置的栅极端子，使得可以向栅极端子施加电压以控制所述沟道的导电性; 以及当没有电压施加到所述栅极端子时，处理所述第一部分和所述第二部分中的至少一个，使得具有大于所述沟道的电导率的导电性。在某些实施例中，处理包括将第一和第二部分中的至少一个暴露于电磁辐射。第一和第二部分可以被激光退火以增加它们的电导率。

10. 发明授权

US09130179B2 Electronic devices 有权
标题翻译：电子设备
公开(公告)号：US09130179B2
公开(公告)日：2015-09-08
申请号：US13988399
申请日：2011-11-25
申请人： Martin Jackson , Catherine Ramsdale , Jerome Joimel
发明人： Martin Jackson , Catherine Ramsdale , Jerome Joimel
IPC分类号： H01L51/05 , H01L27/28
CPC分类号： H01L51/0512 , H01L27/283 , H01L51/0541 , H01L51/0545
摘要： A device comprising an array of transistors, including: patterned conductive layers located at lower and upper levels in a stack of layers on a substrate, which patterned conductive layers define gate conductors and source-drain electrodes of the array of transistors; wherein the stack of layers further comprises a dielectric layer below said lower level, and a further patterned conductive layer below said dielectric layer; and wherein said further patterned conductive layer both provides an electrical function in said array of transistors via said dielectric layer, and defines openings via which the dielectric layer serves to increase the strength of adhesion between the device substrate and the patterned conductive layer at said lower level.
摘要翻译：一种包括晶体管阵列的器件，包括：位于衬底上的层叠层中的下层和上层的图案化导电层，所述图案化导电层限定晶体管阵列的栅极导体和源 - 漏电极; 其中所述层叠层还包括位于所述下层下面的电介质层，以及在所述介电层下方的另外的图案化导电层; 并且其中所述另外的图案化导电层都经由所述介电层在所述晶体管阵列中提供电功能，并且限定开口，所述介电层用于通过所述开口增加所述下层的器件基板和图案化导电层之间的粘合强度。

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